AS3688 datasheet(61/72 Pages) AMSOSRAM

61 / 72 page

AS3688

austriami crosyst ems

Datasheet, Confidential

www.austriamicrosystems.com (ptr,tje)

Revision 1.1.1 / 20060707

59 - 70

Sequential Read is the extended form of Random Read, as multiple register-data bytes are subsequently

transferred.

In contrast to the Random Read, in a sequential read the transferred register-data bytes are responded by an

acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the

behavior of the word-address counter). To terminate the transmission the master has to send a NOT

ACKNOWLEDGE following the last data byte and subsequently generate the STOP condition.

Figure 38 – Serial Interface Current Address Read

data 1

data 2

…

data n

N P

Read Register

WA++

Read Register

WA++

Read Register

WA++

Read Register

WA++

AS3688 (= slave) receives data

AS3688 (= slave) transmits data

To keep the access time as small as possible, this format allows a read access without the word address transfer

in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-

Read address.

Analogous to Random Read, a single byte transfer is terminated with a NOT ACKNOWLEDGE after the 1st

data bytes must be responded to with an ACKNOWLEDGE from the master.

For termination of the transmission the master sends a NOT ACKNOWLEDGE following the last data byte and a

subsequent STOP condition.

7.11 Operating Modes

If the voltage on VDD_GPIO is less than 0.3V, the AS3688 is in shutdown mode and its current consumption is

minimized (I(BAT) = ISHUTDOWN) and all internal registers are reset to their default values and the serial interface

is disabled.

If the voltage on VDD_GPIO rises above 1.5V, the AS3688 serial interface is enabled and the AS3688 and the

standby mode is selected.

If the LDO ANA1 is enabled (ldo_ana1_on=1) and ldo_ana1_lpo is set, the AS3688 enters low power mode

(I(BAT) = ILOWPOWER).

The AS3688 is switched automatically from standby mode (I(BAT) = ISTANDBY) or low power mode into normal

mode (I(BAT) = IACTIVE) and back, if one of the following blocks are activated:

LDO ANA1 in normal mode (ldo_ana1_lpo=0)

LDO ANA2

Charge pump

External charge pump

Step up regulator

Any current sink

ADC conversion started

PWM active

Pattern mode active.

If any of these blocks are already switched on (active mode) the internal oscillator is running and a write

instruction to the registers is directly evaluated within 1 internal CLK Cycle (Typ. 1usec)

If all these blocks are disabled (standby mode or lowpower mode), a write instruction to enable these blocks is

delayed by 64 CLK cycles (oscillator will startup, within max 200usec).

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