AS1181 datasheet(64/92 Pages) AMSOSRAM

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AS1181

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DS001139 • v3-00 • 2026-Apr-01

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8.3.19

CH_DLY register (Address 0x1A24)

Table 31: CH_DLY register (Write Access when system state == idle)

Addr: 0x1A24

CH_DLY

Bit

Bit field

Default

Access

Bit description

9:0

td_trigdly

OTP

Trigger delay [μs]

000h: 45µs

…

02Dh: 45µs

064h: 100µs

3FFh: 1024µs

Note: Values < 45 are internally limited to a minimum of 45 [µs]

13:10

td_stagger

OTP

Channel-to-channel delay for all channels in trigger group 0

Step size 1 µs

8.3.20

CH_ENABLE register (Address 0x1A26)

Table 32: CH_ENABLE register (Write Access when system state == idle)

Addr: 0x1A26

CH_ENABLE

Bit

Bit field

Default

Access

Bit description

7:0

Chan_enable

OTP

Channel enable vector, bit n enables channel [n]

8.3.21

LED_CONFIG register (Address 0x1A28)

Table 33: LED_CONFIG register (Write Access when system state == idle)

Addr: 0x1A28

LED_CONFIG

Bit

Bit field

Default

Access

Bit description

7:0

Led_config

OTP

LED configuration per channel

1-LED

2-LEDs

led_fb_ov_mask

OTP

Masks overvoltage detection for all channels

configured as 1-LED channel

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