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AS7341L 数据表(PDF) 33 Page - ams-OSRAM AG |
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AS7341L 数据表(HTML) 33 Page - ams-OSRAM AG |
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33 / 65 page ![]() Document Feedback AS7341L Register Description Datasheet • PUBLIC DS000718 • v1-00 • 2020-May-25 64 │ 32 10.2.2 ADC Timing Configuration / Integration Time The integration time in INT_MODE = “00” and “01” (SPM/SYNS) is set using the ATIME (0x81) and ASTEP (0xCA, 0xCB) registers. The integration time, in milliseconds, is equal to: Equation 1: Setting the Integration Time ������������������������ = (������������������������������ + 1) × (������������������������������ + 1) × 2.78µ������ The reset value for ASTEP is 999 (2.78 ms) and the recommended configuration for these two registers is ASTEP = 599 and ATIME = 29, which results in an integration time of 50 ms. It is not allowed that both settings –ATIME and ASTEP – are set to “0”. The integration time also defines the full-scale ADC value, which is equal to: Equation 2: ADC Full Scale Value ������������������������������������������������������������������������ = (������������������������������ + 1) × (������������������������������ + 1) ATIME Register (Address 0x81) Figure 39: ATIME Register Addr: 0x81 ATIME Bit Bit Name Default Access Bit Description 7:0 ATIME 0x00 RW Integration time. Sets the number of integration steps from 1 to 256. Value Integration Time 0 ASTEP n ASTEP x (n+1) 255 256 x ASTEP |
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