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db12348e_V3.11_preliminary_2017-07-06

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AS89010

V3.11

Figure 11: I²C bus data transfer

1

2

8

9

R/W

ACK

1

2

8

9

ACK

DATA

7

SLAVE ADDRESS

Sr or P

slave acknowledge

receiver acknowledge

1 1 1 0 1 A1 A0

S or Sr

Figure 12: Write and read data sequences

S SLAVE ADDR. R/W A

0

REG ADDR.

A

DATA

A

DATA

A

P

write sequence:

. . .

S SLAVE ADDR. R/W A

0

REG ADDR.

A

DATA

A

DATA

NA P

read sequence:

. . .

Sr SLAVE ADDR. R/W

1

data transfered from slave to master

data transfered from master to slave

A:

acknowledge

NA: not acknowledge

S: start cond.

Sr: repeated start cond.

P: stop cond.

A

5.6.1 Write Protocol

The start byte consists of the slave address, followed by

W

R/

set to set to ‘0’ for the write direction. The

first byte after the start byte is always the address pointer to the internal register which the master wants

to write. The device acknowledges this byte (REG ADDR. in Figure 12). If the master generates a stop

condition the transfer is aborted and a new write sequence must be started from the beginning. If master

sends the next byte, this one will be stored in the internal register, addressed by the address pointer (REG

ADDR.). The device sends acknowledge and internally increments the address pointer by 1. Then each next

data byte transferred from the master will be stored sequentially in the internal register.

5.6.2 Read Protocol

The slave address is followed by

W

R/

set to ‘0’ for the write direction. The first transferred byte after the

start byte is always the address pointer to the internal register the master wants to read. The device

acknowledges this byte (REG ADDR. see Figure 12). The master sends a repeated start condition and

repeats the slave address but with the

W

R/

bit reversed. The slave acknowledges this byte and starts the

data transfer to the master. The first transferred byte is the content of the internal register which is pointed

by address pointer. Each transferred byte is acknowledged by the master. If not acknowledge occurs the

master sends as next the stop condition and the transfer is finished. Internal address pointer increments

carries out that the subsequent transferred data are sequentially read out from internal register.