301020013 datasheet(49/109 Pages) AMSOSRAM

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Address: 0x01

Default value: 0xA8

Access: Read/Write

Bit

Bit name

Default value

Bit description

0:0

Update Request

In order to activate a set of new register values

uploaded over SPI, this bit has to be set to 1. Register

data does not change unless this bit was set to 1 and

a rising edge of End ADC occurred. When this bit is

set, at the next rising edge of End ADC signal the

(1) The 13th bit should be ignored if on chip saturation is enabled, it holds an overflow identification flag in this case.

(2) It is recommended to configure ADC resolution to 12 bits, enable saturation set to ‘1’ and End of Range Register (register

0x09) to 0x80H, which allows for an output of 4095DN.

(3) The digital subtraction feature enabled (bit set to ‘1’) is not recommended, creating artifacts in the image. Still, if using this

feature, the bit 2 in Control Register 3 (register 0x05) "Enable Offset SRAM" must be set to ‘1’, at user’s responsibility.

Table 17: Clock division

Bit 2

Bit 1

Description

Readout clock set to MCLK

Readout clock set to MCLK/2

ADC CLK remains at MCLK

Readout clock set to MCLK/4

ADC CLK remains at MCLK

Do not use, clock not generated

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