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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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R5F572MNDDFC 数据表(PDF) 91 Page - Renesas Technology Corp |
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R5F572MNDDFC 数据表(HTML) 91 Page - Renesas Technology Corp |
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91 / 180 page  R01DS0332EJ0120 Rev.1.20 Page 91 of 180 Nov 15, 2023 RX72M Group 2. Electrical Characteristics 2.4.2 Clock Timing Figure 2.3 BCLK Pin and SDCLK Pin Output Timing Table 2.14 BCLK Pin Output, SDCLK Pin Output Clock Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item Symbol Min. Typ. Max. Unit Test Conditions BCLK pin output cycle time tBcyc 12.5 — — ns Figure 2.3 BCLK pin output high pulse width tCH 3.25 — — ns BCLK pin output low pulse width tCL 3.25 — — ns BCLK pin output rising time tCr —— 3 ns BCLK pin output falling time tCf —— 3 ns SDCLK pin output cycle time tBcyc 12.5 — — ns SDCLK pin output high pulse width tCH 3.25 — — ns SDCLK pin output low pulse width tCL 3.25 — — ns SDCLK pin output rising time tCr —— 3 ns SDCLK pin output falling time tCf —— 3 ns tCf tCH tBcyc, tSDcyc tCr tCL BCLK pin output, SDCLK pin output Test conditions: VOH = 0.7 × VCC, VOL = 0.3 × VCC, C = 30 pF |
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