 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
R5F572MNDDFC 数据表(PDF) 97 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
R5F572MNDDFC 数据表(HTML) 97 Page - Renesas Technology Corp |
|
|
97 / 180 page  R01DS0332EJ0120 Rev.1.20 Page 97 of 180 Nov 15, 2023 RX72M Group 2. Electrical Characteristics 2.4.3 Timing of Recovery from Low Power Consumption Modes Note 1. The time for recovery from software standby mode is determined by the value obtained by adding the oscillation stabilization waiting time (tSBYOSCWT) and the time required for operations by the software standby release sequencer (tSBYSEQ). Note 2. When several oscillators were running before the transition to software standby, the greatest value of the oscillation stabilization waiting time tSBYOSCWT is selected. Note 3. For n, the greatest value is selected from among the internal clock division settings. Note 4. This condition applies when fICLK:fFCLK = 1:1, 2:1, or 4:1. Table 2.23 Timing of Recovery from Low Power Consumption Modes (1) Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item Symbol Min. Typ. Max. Unit Test Conditions tSBYOSCWT*2 tSBYSEQ*3 Recovery time from software standby mode *1 Crystal resonator connected to main clock oscillator Main clock oscillator operating tSBYMC — — {(MSTS[7:0] bit × 32) + 76} / 0.216 100 + 7 / fICLK + 2n / fMAIN µs Figure 2.14 Main clock oscillator and PLL circuit operating tSBYPC {(MSTS[7:0] bit × 32) + 138} / 0.216 100 + 7 / fICLK + 2n / fPLL External clock input to main clock oscillator Main clock oscillator operating tSBYEX 352 100 + 7 / fICLK + 2n / fEXMAIN Main clock oscillator and PLL circuit operating tSBYPE 639 100 + 7 / fICLK + 2n / fPLL Sub-clock oscillator operating tSBYSC {(SSTS[7:0] bit × 16384) + 13} / 0.216 + 10 / fFCLK 100 + 4 / fICLK + 2n / fSUE High-speed on-chip oscillator operating High-speed on-chip oscillator operating tSBYHO 454 100 + 7 / fICLK + 2n / fHOCO High-speed on-chip oscillator operating and PLL circuit operating tSBYPH 741 100 + 7 / fICLK + 2n / fPLL Low-speed on-chip oscillator operating*4 tSBYLO 338 100 + 7 / fICLK + 2n / fLOCO |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
