MK50H25 datasheet(1/64 Pages) STMICROELECTRONICS

部件名	MK50H25

功能描述	HIGH SPEED LINK LEVEL CONTROLLER

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制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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MK50H25

HIGH SPEED

LINK LEVEL CONTROLLER

ADVANCE DATA

SECTION 1 - FEATURES

System clock rate up to 33 MHz (MK50H25 -

33), 25 MHz (MK50H25 - 25), or 16 MHz

(MK50H25 - 16).

Data

rate

up

to

20

Mbps

continuous

(MK50H25 - 33) or up to 51 Mbps bursted

On chip DMA control with programmable burst

length.

DMA transfer rate of up to 13.3 Mbytes/sec us-

ing optional 5 SYSCLK DMA cycle (150 nS) at

33 MHz SYSCLK.

Complete Level 2 implementation compatible

with X.25 LAPB, ISDN LAPD, X.32, and X.75

Protocols.

Handles all error recovery, sequencing, and S

and U frame control.

Pin-for-pin and architecturally compatible with

MK5025 (X.25/LAPD), MK5027 (CCS#7) and

MK5029(SDLC).

Buffer Management includes:

- Initialization Block

- Separate Receive and Transmit Rings

- Variable Descriptor Ring and Window Sizes.

Separate 64-byte Transmit and Receive FIFO.

Programmable Transmit FIFO hold-off water-

mark.

Handles all HDLC frame formatting:

- Zero bit insertion and deletion

- FCS (CRC) generation and detection

- Frame delimiting with flags

Programmable Single or Extended Address

and Control fields.

Five programmable timer/counters:

T1, T3,

TP, N1, N2

Programmable minimum frame spacing on

transmission

(number

of

flags

between

frames).

- Programmable from 1 to 62 flags between

frames

Selectable FCS (CRC) of 16 or 32 bits, and

passing of entire FCS to buffer.

Testing Facilities:

- Internal Loopback

- Silent Loopback

- Optional Internal Data Clock Generation

- Self Test.

Programmable for full or half duplex operation

Programmable Watchdog Timers for RCLK

and TCLK (to detect absence of data clocks)

Option causing received data to effectively be

odd-byte aligned, in addition to standard even-

byte alignment.

Available in 52 pin PLCC, 84 pin PLCC(for use

with external ROM), or 48 pin DIP packages.

SECTION 2 - INTRODUCTION

The SGS - Thomson MK502H5 Link Level Con-

troller is a VLSI semiconductor device which pro-

vides complete link level data communications

control conforming to the 1984 and 1988 CCITT

versions of X.25. The MK50H25 will perform

frame formating including: frame delimiting with

flags, transparency (so-called ”bit-stuffing”), error

recovery by retransmission, sequence number

control, S (supervisory) and U (unnumbered)

frame control, plus FCS (CRC) generation and

detection. The MK50H25 also supports X.75 and

X.32 (with its XID frame support), as well as sin-

gle channel ISDN LAPD (with its support of UI

frames and extended addressing capabilities).

July 1994

DIP48

PLCC 52

1/64

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