MK50H25 datasheet(21/64 Pages) STMICROELECTRONICS

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of the XID command is located in the XID/TEST Receive buffer.

Valid only if XIDE bit in CSR2 is set.

XID Confirmation: Indicates the receipt of an XID response. The data

field of the XID command is located in the XID/TEST Receive buffer.

Valid only if XIDE bit in CSR2 is set.

TEST Indication: Indicates the receipt of TEST command. The data field

of the TEST command is located in the XID/TEST Receive buffer.

TEST Confirmation: Indicates the receipt of an TEST response. The data

field of the XID command is located in the XID/TEST Receive buffer.

Valid only if XIDE bit in CSR2 is set.

Disconnect Indication: Indicates request by the remote station to disconnect

the current logical link (DISC received), or the refusal of a previous

Connect or Reset Request. The chip is now in the Disconnected

phase.

Disconnect Confirmation: Indicates the completion of a previously

requested link disconnection.

4.1.2.3 Control and Status Register 2 (CSR2)

RAP<3:1> = 2

BIT

NAME

DESCRIPTION

CYCLE

Setting this bit selects a shorter DMA cycle (5 vs 6 SYSCLKs for bursting

or 5 vs 7 SYSCLKs for single DMA). See Figures 7a and 8a for details.

EIBEN

Extended Initialization Block Enable. Setting this bit will cause the

MK50H25 to use an extended Initialization Block which uses all of

IADR+08 as a 16-bit scaler, moves N2 to the upper byte of IADR+40,

and extends the Init Block past IADR+55. This bit is READ/WRITE.

FRMRD

Setting this bit disables the sending of FRMR frames (used for LAPD

applications); otherwise the MK50H25 behaves as specified for X.25.

This bit is READ/WRITE.

T203E

If this bit is set, the T3 timer is reconfigured to behave as specified for

LAPD T203 timer; otherwise it behaves as specified for X.25. The op-

eration of the T203 timer is that it expires after T203 time of not having

received any type of frame, and causes a RR/P=1 polling (Timer Re-

covery) procedure to begin. This bit is READ/WRITE.

X75E

X.75 mode of protocol operation is enabled if this bit is set to 1;

otherwise X.25 mode is enabled. This bit is READ/WRITE.

PROM

Address filtering is disabled for Transparent Mode if this bit is set. All

uncorrupted incomming frames are placed in the Receive Descriptor

Ring. This bit is READ/WRITE and should be set only in Transparent

Mode.

UIE

UI frames are recognized only if this bit is set. If UIE=0 all received UI

frames will not be recognized. This bit is READ/WRITE.

XIDE

XID frames are recognized only if this bit is set. If XIDE=0 all received

XID frames will not be recognized. This bit is READ/WRITE.

IADR<23:16>

MK50H25

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