M9346-RBN3T datasheet(15/34 Pages) STMICROELECTRONICS

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M93S66, M93S56, M93S46

ing the Protection Register Write (PRWRITE) in-

struction. When the OTP bit is set, the Ready/Busy

status cannot appear on Serial Data Output (Q).

When the OTP bit is not set, the Busy status ap-

pears on Serial Data Output (Q).

Note: A Protection Register Enable (PREN) in-

struction must immediately precede the Protection

COMMON I/O OPERATION

Serial Data Output (Q) and Serial Data Input (D)

can be connected together, through a current lim-

iting resistor, to form a common, single-wire data

bus. Some precautions must be taken when oper-

ating the memory in this way, mostly to prevent a

short circuit current from flowing when the last ad-

dress bit (A0) clashes with the first data bit on Se-

rial Data Output (Q). Please see the application

note AN394 for details.

Figure 8. Write Sequence with One Clock Glitch

CLOCK PULSE COUNTER

In a noisy environment, the number of pulses re-

ceived on Serial Clock (C) may be greater than the

number delivered by the Bus Master (the micro-

controller). This can lead to a misalignment of the

instruction of one or more bits (as shown in Figure

8.) and may lead to the writing of erroneous data

at an erroneous address.

To combat this problem, the M93Sx6 has an on-

chip counter that counts the clock pulses from the

start bit until the falling edge of the Chip Select In-

put (S). If the number of clock pulses received is

not the number expected, the WRITE, PAWRITE,

WRALL, PRWRITE or PRCLEAR instruction is

aborted, and the contents of the memory are not

modified.

The number of clock cycles expected for each in-

struction, and for each member of the M93Sx6

family, are summarized in Table 2. to Table 3.. For

example, a Write Data to Memory (WRITE) in-

struction on the M93S56 (or M93S66) expects 27

clock cycles from the start bit to the falling edge of

Chip Select Input (S). That is:

1 Start bit

+ 2 Op-code bits

+ 8 Address bits

+ 16 Data bits

AI01395

An-1

WRITE

START

"1"

"0"

Glitch

An-2

ADDRESS AND DATA

ARE SHIFTED BY ONE BIT

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