9DB433

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

IDT®

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

7

9DB433

MAY 25, 2018

Electrical Characteristics–PCIe Phase Jitter Parameters

Clock Periods–Differential Outputs Tracking Spread Spectrum

TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

INDUSTRY

LIMIT

UNITS Notes

tjphPCIeG1

PCIe Gen 1

26

40

86

ps

(p-p)

1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.8

1.2

3

ps

(rms)

1,2

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

1.6

1.8

3.1

ps

(rms)

1,2

tjphPCIeG3

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

0.48

0.6

1

ps

(rms)

1,2,4

tjphPCIeG1

PCIe Gen 1

2.6

5

N/A

ps (p-p) 1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.06

0.2

N/A

ps

(rms)

1,2

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

0.3

N/A

ps

(rms)

1,2

tjphPCIeG3

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

0.1

N/A

ps

(rms)

1,2

1 Applies to all outputs.

tjphPCIeG2

2 See http://www.pcisig.com for complete specs

tjphPCIeG2

Phase Jitter, PLL Mode

Additive Phase Jitter,

Bypass Mode

3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.

1 Clock

1us

0.1s

0.1s

0.1s

1us

1 Clock

Lg-

-SSC

-ppm error

0ppm

+ ppm error

+SSC

Lg+

Absolute

Period

Short-term

Average

Long-Term

Average

Period

Long-Term

Average

Short-term

Average

Period

Minimum

Absolute

Period

Minimum

Absolute

Period

Minimum

Absolute

Period

Nominal

Maximum

Maximum

Maximum

9.949

9.999

10.024

10.025

10.026

10.051

10.101

ns

1,2,3

Symbol

DIF 100

Notes

Definition

Units

Measurement

Window