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9DB433AFILF 数据表(PDF) 1 Page - Renesas Technology Corp |
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9DB433AFILF 数据表(HTML) 1 Page - Renesas Technology Corp |
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1 / 18 page ![]() DATASHEET FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3 9DB433 IDT® FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3 1 9DB433 MAY 25, 2018 Description The 9DB433 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB433 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. Typical Applications 4 output PCIe Gen1–3 zero-delay/fanout buffer Key Specifications • Output cycle-cycle jitter <50ps • Output to Output skew <50ps • Phase jitter: PCIe Gen3 <1.0ps rms Features • 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tracks spreading input clock for low EMI • SMBus interface; unused outputs can be disabled • Supports undriven differential outputs in Power Down mode for power management Output Features • 4 0.7V current-mode differential HCSL output pairs • Supports zero delay buffer mode and fanout mode • Selectable bandwidth • 50–110MHz operation in PLL mode • 5–166MHz operation in Bypass mode Block Diagram STOP LOGIC SRC_IN SRC_IN# DIF(6,5,2,1) CONTROL LOGIC BYP#_LOBW_HIBW SMBDAT SMBCLK PD# SPREAD COMPATIBLE PLL 4 IREF M U X OE(6,1)# 2 |
类似零件编号 - 9DB433AFILF |
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类似说明 - 9DB433AFILF |
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