9DB833

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

IDT®

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

4

9DB833

MAY 25, 2018

Pin Descriptions (cont.)

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

25

GND

GND

Ground pin.

26

GND

GND

Ground pin.

27

VDD

PWR

Power supply, nominally 3.3V.

28

SMB_ADR_tri

IN

SMBus address select bit. This is a tri-level input that decodes 1 of 3 SMBus

Addresses.

29

DIF_4#

OUT

HCSL complementary clock output.

30

DIF_4

OUT

HCSL true clock output.

31

VDD

PWR

Power supply, nominally 3.3V.

32

GND

GND

Ground pin.

33

DIF_5#

OUT

HCSL complementary clock output.

34

DIF_5

OUT

HCSL true clock output.

35

OE5#

IN

Active low input for enabling output 5.

1 = disable output, 0 = enable output.

36

OE6#

IN

Active low input for enabling output 6.

1 = disable output, 0 = enable output.

37

DIF_6#

OUT

HCSL complementary clock output.

38

DIF_6

OUT

HCSL true clock output.

39

VDD

PWR

Power supply, nominally 3.3V.

40

PD#

IN

Asynchronous active low input pin used to power down the device. The internal

clocks are disabled and the VCO's (if any) and the XTAL oscillator are stopped.

41

DIF_7#

OUT

HCSL complementary clock output.

42

DIF_7

OUT

HCSL true clock output.

43

OE4#

IN

Active low input for enabling output 4

1 = disable output, 0 = enable output.

44

OE7#

IN

Active low input for enabling output 7.

1 = disable output, 0 = enable output.

45

LOCK

OUT

3.3V output indicating PLL Lock Status. This pin goes high when lock is

achieved.

46

IREF

OUT

This pin establishes the reference for the differential current-mode output pairs. It

requires a fixed precision resistor to ground. 475ohm is the standard value for

100ohm differential impedance. Other impedances require different values. See

data sheet.

47

GNDA

GND

Ground pin for the PLL core.

48

VDDA

PWR

Power supply for PLL core.