9DB833

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

IDT®

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

2

9DB833

MAY 25, 2018

Pin Configuration

Operating Mode Readback Table

Power Connections

Tri-level Input Logic Levels

SMBus Address Selection and Readback

SRC _DIV# 1

48 VDDA

VDD R 2

47 GNDA

GN D 3

46 IR EF

SRC_IN 4

45 LOCK

SRC_IN# 5

44 OE7#

OE0# 643 OE4#

OE3# 742 DIF_7

DIF_0 8

41 DIF_7#

DIF_0# 940 PD#

GN D 10

39 VDD

VD D 11

38 DIF_6

DIF_1 12

37 DIF_6#

DIF_1# 13

36 OE6#

OE1# 14

35 OE5#

OE2# 15

34 DIF_5

DIF_2 16

33 DIF_5#

DIF_2# 17

32 GND

GN D 18

31 VDD

VD D 19

30 DIF_4

DIF_3 20

29 DIF_4#

DIF_3# 21

28 SMB_A DR_tri

BYP#_HIBW_LOBW 22

27 VDD

SMBCLK 23

26 GND

SMBDAT 24

25 GND

Notes:

Highlighted Pins are the differences between 9DB803 and 9DB833.

Pin 22 and Pin 28 are latched on power up. Please make sure that the

power supply to the pullup/pulldown resistors ramps at the same time

as the main supply to the chip.

BYP#_LOB W_HIBW

MODE

Byte0, bit 3 Byte 0 bit 1

Low

Bypass

0

0

Mid

PLL 100M H i BW

1

0

High

PLL 100M Low BW

0

1

VDD

GND

2

3

SRC_IN/SRC_IN#

11,19,31,39

10,18, 25,32

DIF(7:0)

27

26

DIGITAL VDD/GND

48

47

Analog VDD/GND for PLL in IREF

For best results, treat pin 2 as analog VDD.

Description

Pin Number

State of Pin

Voltage

Low

<0.8V

Mid

1.2<Vin<1.8V

High

Vin > 2.0V

SMB_AD R_tri

Address

Low

DA/DB

Mid

D C/DD

High

D8/D9