HT46C46 datasheet(29/77 Pages) HOLTEK

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HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.30

June 5, 2008

fSYS

A/D Clock Period (tAD)

ADCS1, ADCS0=00

(fSYS/2)

ADCS1, ADCS0=01

(fSYS/8)

ADCS1, ADCS0=10

(fSYS/32)

ADCS1, ADCS0=11

1MHz

ms8ms32ms

Undefined

2MHz

ms4ms16ms

Undefined

4MHz

500ns*

ms8ms

Undefined

8MHz

250ns*

ms4ms

Undefined

A/D Clock Period Examples

A/D Input Pins

All of the A/D analog input pins are pin-shared with the

I/O pins on Port B. Bits PCR2~PCR0 in the ADCR regis-

ter, not configuration options, determine whether the in-

put pins are setup as normal Port B input/output pins or

whether they are setup as analog inputs. In this way, pins

can be changed under program control to change their

function from normal I/O operation to analog inputs and

vice versa. Pull-high resistors, which are setup through

configuration options, apply to the input pins only when

they are used as normal I/O pins, if setup as A/D inputs

the pull-high resistors will be automatically disconnected.

Note that it is not necessary to first setup the A/D pin as

an input in the PBC port control register to enable the A/D

input, when the PCR2~PCR0 bits enable an A/D input,

the status of the port control register will be overridden.

The VDD power supply pin is used as the A/D converter

reference voltage, and as such analog inputs must not be

allowed to exceed this value. Appropriate measures

should also be taken to ensure that the VDD pin remains

as stable and noise free as possible.

Initialising the A/D Converter

The internal A/D converter must be initialised in a spe-

cial way. Each time the Port B A/D channel selection bits

are modified by the program, the A/D converter must be

re-initialised. If the A/D converter is not initialised after

the channel selection bits are changed, the EOCB flag

may have an undefined value, which may produce a

false end of conversion signal. To initialise the A/D con-

verter after the channel selection bits have changed,

then, within a time frame of one to ten instruction cycles,

the START bit in the ADCR register must first be set high

and then immediately cleared to zero. This will ensure

that the EOCB flag is correctly set to a high condition.

Summary of A/D Conversion Steps

The following summarizes the individual steps that

should be executed in order to implement an A/D con-

version process.

· Step 1

Select the required A/D conversion clock by correctly

programming bits ADCS1 and ADCS0 in the ACSR

· Step 2

Select which channel is to be connected to the internal

A/D converter by correctly programming the

ACS2~ACS0 bits which are also contained in the

ADCR register.

· Step 3

Select which pins on Port B are to be used as A/D in-

puts and configure them as A/D input pins by correctly

programming the PCR2~PCR0 bits in the ADCR reg-

ister. Note that this step can be combined with Step 2

into a single ADCR register programming operation.

· Step 4

If the interrupts are to be used, the interrupt control

registers must be correctly configured to ensure the

A/D converter interrupt function is active. The master

interrupt control bit, EMI, in the INTC interrupt control

²1² and the A/D converter inter-

rupt bit, EADI, in the INTC register must also be set to

²1².

· Step 5

The analog to digital conversion process can now be

initialised by setting the START bit in the ADCR regis-

ter from

²0² to ²1² and then to ²0² again. Note that this

bit should have been originally set to

²0².

· Step 6

To check when the analog to digital conversion pro-

cess is complete, the EOCB bit in the ADCR register

can be polled. The conversion process is complete

when this bit goes low. When this occurs the A/D data

registers ADRL and ADRH can be read to obtain the

conversion value. As an alternative method if the in-

terrupts are enabled and the stack is not full, the pro-

gram can wait for an A/D interrupt to occur.

Note:

When checking for the end of the conversion

process, if the method of polling the EOCB bit in

the ADCR register is used, the interrupt enable

step above can be omitted.

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