HT46C46 datasheet(35/77 Pages) HOLTEK

35 / 77 page

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.30

June 5, 2008

A u t o m a t i c a l l y C l e a r e d b y I S R

M a n u a l l y S e t o r C l e a r e d b y S o f t w a r e

E x t e r n a l I n t e r r u p t

R e q u e s t F l a g E I F

T i m e r / E v e n t C o u n t e r

I n t e r r u p t R e q u e s t F l a g T F

E E I

E T I

E M I

P r i o r i t y

I n t e r r u p t

P o l l i n g

H i g h

L o w

A u t o m a t i c a l l y D i s a b l e d b y I S R

C a n b e E n a b l e d M a n u a l l y

E A D I

A / D C o n v e r t e r

I n t e r r u p t R e q u e s t F l a g A D F

Interrupt Structure

related interrupt is enabled, until the Stack Pointer is

decremented. If immediate service is desired, the stack

must be prevented from becoming full.

Interrupt Priority

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In case of simultaneous requests,

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

Interrupt Source

All Devices Priority

External Interrupt

Timer/Event Counter Overflow

A/D Converter Interrupt

In cases where both external and internal interrupts are

enabled and where an external and internal interrupt oc-

curs simultaneously, the external interrupt will always

have priority and will therefore be serviced first. Suitable

masking of the individual interrupts using the INTC reg-

ister can prevent simultaneous occurrences.

External Interrupt

For an external interrupt to occur, the global interrupt en-

able bit, EMI, and external interrupt enable bit, EEI, must

first be set. An actual external interrupt will take place

when the external interrupt request flag, EIF, is set, a situ-

ation that will occur when a high to low transition appears

on the INT line. The external interrupt pin is pin-shared

with the I/O pin PA5 and can only be configured as an ex-

ternal interrupt pin if the corresponding external interrupt

enable bit in the INTC register has been set. The pin must

also be setup as an input by setting the corresponding

PAC.5 bit in the port control register. When the interrupt is

enabled, the stack is not full and a high to low transition

appears on the external interrupt pin, a subroutine call to

the external interrupt vector at location 04H, will take

place. When the interrupt is serviced, the external inter-

rupt request flag, EIF, will be automatically reset and the

EMI bit will be automatically cleared to disable other inter-

rupts. Note that any pull-high resistor configuration op-

tions on this pin will remain valid even if the pin is used as

an external interrupt input.

Timer/Event Counter Interrupt

For a Timer/Event Counter interrupt to occur, the global

interrupt enable bit, EMI, and the corresponding timer

interrupt enable bit, ETI, must first be set. An actual

Timer/Event Counter interrupt will take place when the

Timer/Event Counter request flag, TF, is set, a situation

that will occur when the Timer/Event Counter overflows.

When the interrupt is enabled, the stack is not full and a

Timer/Event Counter overflow occurs, a subroutine call

to the timer interrupt vector at location 08H, will take

place. When the interrupt is serviced, the timer interrupt

request flag, TF, will be automatically reset and the EMI

bit will be automatically cleared to disable other inter-

rupts.

A/D Interrupt

For an A/D interrupt to occur, the global interrupt enable

bit, EMI, and the corresponding interrupt enable bit,

EADI, must be first set. An actual A/D interrupt will take

place when the A/D converter request flag, ADF, is set, a

situation that will occur when an A/D conversion process

has completed. When the interrupt is enabled, the stack

is not full and an A/D conversion process finishes exe-

cution, a subroutine call to the A/D interrupt vector at lo-

cation 0CH, will take place. When the interrupt is

serviced, the A/D interrupt request flag, ADF, will be au-

tomatically reset and the EMI bit will be automatically

cleared to disable other interrupts.

Programming Considerations

By disabling the interrupt enable bits, a requested inter-

rupt can be prevented from being serviced, however,

once an interrupt request flag is set, it will remain in this

condition in the INTC register until the corresponding in-

terrupt is serviced or until the request flag is cleared by a

software instruction.

It is recommended that programs do not use the

²CALL

subroutine

² instruction within the interrupt subroutine.

Interrupts often occur in an unpredictable manner or

need to be serviced immediately in some applications. If

only one stack is left and the interrupt is not well con-

trolled, the original control sequence will be damaged

once a

²CALL subroutine² is executed in the interrupt

subroutine.

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