Timing

RHF1401

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3

Timing

Table 2.

Timing characteristics

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

1.

See clock recommendations in Section 7.2: Clock signal requirements on page 19

1.5

20

MHz

Sampling clock cycle(1)

50

667

ns

DC

Clock duty cycle

50

%

Clock pulse width (high)

25

ns

Clock pulse width (low)

25

ns

Data output delay (fall of

2.

See Figure 3 and discussion below.

10 pF load capacitance

5

7.5

13

ns

Data pipeline delay

8.5

8.5

8.5

cycles

Data ready rising edge

delay after data change

0.5

cycles

Falling edge of OEB to

digital output valid data

1ns

Rising edge of OEB to

digital output tri-state

1ns

Data rising time

10 pF load capacitance

6

ns

Data falling time

10 pF load capacitance

3

ns