RHF1401 datasheet(21/29 Pages) STMICROELECTRONICS

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RHF1401

Application information

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Figure 24.

Impact of clock frequency on RHF1401 performance

In the case of under-sampling, that is when the sampling rate is much lower than the input

signal frequency (for example a 2Msps sampling rate with a 41.3MHz input signal), there are

two critical parameters to consider:

●

The value of the Rpol resistor

●

The clock jitter

7.5

Digital inputs/outputs

Data format select (DFSB)

When set to low level (VIL), the digital input DFSB provides a two’s complement digital

output MSB. This can be of interest when performing further signal processing.

When set to high level (VIH), DFSB provides a standard binary output coding.

Output enable (OEB)

When set to low level (VIL), all digital outputs remain active and are in low impedance state.

When set to high level (VIH), all digital output buffers are in high impedance state. It results

in lower consumption while the converter goes on sampling.

When OEB is set to low level again, the data is then delivered on the output with a very short

Ton delay.

Out of range (OR)

This function is implemented on the output stage in order to set up an “Out of range” flag

whenever the digital data is over the full scale range.

Typically, there is a detection of all the data at ’0’ or all the data at ’1’. This ends up with an

output signal OR which is in low level state (VOL) when the data is within the range, or in

high level state (VOH) when the data is out of the range.

Fin

Fs = 1.0 Msps

Fs = 1.2 Msps

Fs = 1.5 Msps

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