User Guide

EVAL-AD5766ARDZ/EVAL-AD5767ARDZ

EVALUATION BOARD HARDWARE

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Rev. 0 | 4 of 17

ADP5071 POWER SOLUTION OPTION

The EVAL-AD5766ARDZ/EVAL-AD5767ARDZ evaluation boards

are populated with the ADP5071 switching regulator. This regulator

generates +8 V and −22 V supplies. The ADP5071 data sheet

recommends 3.3 V for correct operation.

Two ways to power the ADP5071 are available using the

PWR_SEL options. First, use an external 3.3 V supply (recom-

mended). This method involves connecting an external 3.3 V sup-

ply, which provides a stable and reliable power source, especially

for more demanding applications. This method is recommended for

most cases to ensure optimal performance. The other option is by

using the SDP-K1 as the power supply.

To select the power source for AVCC, use the AVCC_SEL jumper.

Position 1-2 on AVCC_SEL ties AVCC and the ADP5071 supplies

together to operate from a single 3.3 V supply. Alternatively, Posi-

tion 2-3 on AVCC_SEL powers AVCC with an external supply via the

EXT_AVCC connector. Refer to Table 3 for all the link options. Note

that the −12 V to +14 V, −16 V to +10 V, or −10 V to +10 V output

voltage ranges are not available with the default configuration of the

ADP5071 because a minimum of 2 V headroom is required.

Table 3. Link Options

Link Options

Description

AVCC_SEL

Selects the power supply for the DAC AVCC pin; requires 2.97 V to 3.6 V for correct operation

Position 1-2: supplied by PWR_SEL connector

Position 2-3: supplied by external power supply through the EXT_AVCC connector, see Table 4 for more information

AVDD_SEL

Selects the power supply for the DAC AVDD pin; ensure that the voltage between AVDD and AVSS does not exceed 34 V

Position 1-2: supplied by the ADP5071 power solution

Position 2-3: supplied by an external power supply through the P8 connector

AVSS_SEL

Selects the power supply for DAC AVSS pin; ensure that the voltage between AVDD and AVSS does not exceed 34 V

Position 1-2: supplied by an external power supply through the P8 block

Position 2-3: supplied by the ADP5071 power solution

REF_SEL

Selects the voltage reference source

Position 1-2: selects an external reference source that can applied at the EXT_VREF SMB connector

Position 2-3: selects the ADR4525 2.5 V reference

PWR_SEL

Selects the power supply source

Position 1-2: supplied by an external reference source that can applied at the EXT_3V3 (P7) connector

Position 2-3: supplied by the SDP-K1 controller board

JP1

Selects the switching frequency of the ADP5071; this link is replaced with a 0 Ω resistor to either position

Position A: 2.4 MHz switching frequency

Position B: 1.2 MHz switching frequency

No link inserted: external clock

JP2

Selects the slew rate of the ADP5071 output; this link is replaced with a 0 Ω resistor to either position

Position A: normal slew rate

Position B: slowest slew rate (best noise performance)

No link inserted: fastest slew rate (best efficiency)

JP3

Selects the start-up sequence of the ADP5071 outputs

Position A: positive and negative output rails power up simultaneously when EN2 is high

Position B: positive and negative output rails are sequenced based on the state of the EN1 and EN2 pins

No link inserted: manual enable mode

JP4

Connected and supplied by the AVCC supply