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ADR4525DEZ-R7 数据表(PDF) 9 Page - Analog Devices

部件名 ADR4525DEZ-R7
功能描述  Evaluating the AD5766 or the AD5767, 16-Channel, 16-/12-Bit Voltage Output DenseDACs
PDF  17 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADR4525DEZ-R7 数据表(HTML) 9 Page - Analog Devices

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User Guide
EVAL-AD5766ARDZ/EVAL-AD5767ARDZ
EVALUATION BOARD SOFTWARE
analog.com
Rev. 0 | 9 of 17
Figure 9. Span Selection Window
Table 6. GUI Options1
Label No.
GUI Element
Description
1
Apply Changes
Click this button to submit any changes on the GUI to the hardware of the evaluation boards.
2
Reset Chip
Click this button to issue a hardware reset and revert the software and hardware registers to their default settings.
3
Write to Input Reg
This dropdown menu allows users to write to the input register, write to the input register and the DAC register, or write to the
input register and update all DAC registers.
4
Select output
Channels display. This dropdown menu allows users to select Channel 0 - 3, Channel 4 - 7, Channel 8 - 11, or Channel 12 -
15 for VOUT in the AD5766 Chip tab.
5
Input Register
The user can input data to write to the input register. Note that there is one input register per channel.
6
DAC Register
This is a graphical representation of the DAC register. Note that there is one DAC register per channel.
7
RANGE SET DAC
Click RANGE SET DAC to select the output voltage range from the SPAN SELECTION window (see Figure 9).
8
DAC 0 to DAC 3
Click the DAC x to apply a dither signal or to enable or disable the update for the selected DAC register with data from the
corresponding input register (software load DAC).
9
Signal , Invert, and Scale
These dropdown menus allow users to select the dither options for each channel.
10
16-To-1 MUX
Use this area to select which channel to route to the AD5766/AD5767 MUX_OUT pin.
11
SOFTWARE RESET
Issues a software reset and reverts the software and hardware registers to their default settings.
12
Proceed to Memory Map
Click this button to open the AD5766 Memory Map tab (see Figure 7).
1 See Figure 8



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