PSD511B1 datasheet(9/153 Pages) STMICROELECTRONICS

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PSD5XX Family

Upon each address or logic input change to the PSD, the device powers up from low power

standby for a short time. Then the PSD consumes only the necessary power to deliver new

logic or memory data to its outputs as a response to the input change. After the new

outputs are stable, the PSD latches them and automatically reverts back to standby mode.

The ICC current flowing during standby mode and during DC operation is identical.

The PSD automatically reduces its DC current drain to these low levels and does not

require controlling by the CSI (Chip Select) input. Disabling the CSI pin unconditionally

forces the PSD to standby mode independent of other input transitions.

The only significant power consumption in the PSD occurs during AC operation.

The PSD contains the first architecture to apply Zero-power techniques to memory circuit

blocks as well as logic.

Figure 2 compares PSD Zero-power operation to the operation of a discrete solution.

A standard microcontroller (MCU) bus cycle usually starts with an ALE (or AS) pulse and

the generation of an address. The PSD detects the address transition and powers up for a

short time. The PSD then latches the outputs of the PAD, EPROM and SRAM to the new

values. After finishing these operations, the PSD shuts off its internal power, entering

standby mode. The time taken for the entire cycle is less than the PSD’s “access time.”

The PSD will stay in standby mode if the inputs do not change between bus cycles. In an

alternate system implementation using discrete EPROM, SRAM and other discrete

components, the system will consume operating power during the entire bus cycle. This is

because the chip select inputs on the memory devices are usually active throughout the

entire cycle. The AC power consumption of the PSD may be calculated using the composite

frequency of the MCU address and control inputs, as well as any other logic inputs to the

ZPLD.

NOTE: The ZPSD5XX parts have been rated for a lower standby current (ISB) than the

PSD5XX parts.

5.0

Integrated

Power

Management TM

Operation

ALE

DISCRETE EPROM, SRAM & LOGIC

ADDRESS

EPROM

ACCESS

SRAM

ACCESS

EPROM

ACCESS

ICC

ZPSD

TIME

Figure 2. ZPSD Power Operation vs. Discrete Implementation

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