PSD511B1 datasheet(106/153 Pages) STMICROELECTRONICS

106 / 153 page

PSD5XX Family

103

The Page Register is 4 bits wide and consists of four D flip flops.The outputs of the Register

(PGR0 – PGR3) are connected to the input bus of the ZPLD. By including the four outputs

as inputs to the DPLD, the addressing capability of the microcontroller is increased by a

factor of 16.

Figure 49 shows the Page Register block diagram. Inputs to the four flip flops are connected

to data bus D0-D3. The output of the Register can be read by the microcontroller. The

implemented.

Figure 49. Page Register

DPLD

RS0

GPLD

PPLD

ZPLD

ES0 – 3

PGR0

PGR1

PGR2

PGR3

R/ W

D0 – D3

PAGE

RESET

The PSD5XX has a programmable security bit which offers protection from unauthorized

duplication. When the security bit is set, the contents of the EPROM, the PSD5XX

non-volatile configuration bits and ZPLD data are prevented from being read by EPROM

programmers.

The security bit is set through the PSDsoft Software and is embedded in the compiled

output file. The security bit is UV erasable and a secured part can be erased and then

re-programmed.

10.0

Page

11.0

Security

Protection

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