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PSD511B1 数据表(PDF) 127 Page - STMicroelectronics |
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PSD511B1 数据表(HTML) 127 Page - STMicroelectronics |
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127 / 153 page  NOTES: 1. Any input used to select an internal ZPSD5XX function. 2. In multiplexed mode latched address generated from ADIO delay to address output on any Port. 3. WR timing has the same timing as E, DS, LDS, UDS, WRL, WRH signals. PSD5XX Family 124 -20 -25 EPROM_CMiser Symbol Parameter Conditions Min Max Min Max ON Unit tLVLX ALE or AS Pulse Width 30 30 ns tAVLX Address Setup Time (Note 1) 12 15 ns tLXAX Address Hold Time (Note 1) 12 17 ns tAVWL Address Valid to Leading Edge of WR (Notes 1 and 3) 35 50 ns t SLWL CS Valid to Leading Edge of WR (Note 3) 40 60 ns t DVWH WR Data Setup Time (Note 3) 25 35 ns t WHDX WR Data Hold Time (Note 3) 5 10 ns t WLWH WR Pulse Width (Note 3) 30 30 ns tWHAX Trailing Edge of WR to Address Invalid (Note 3) 0 0 ns tWHPV Trailing Edge of WR to Port Output Valid (Note 3) 50 60 ns In 16-Bit Data Bus 40 60 ns Address Input Valid to Mode (Note 2) tAVPV Address Output Delay In 8-Bit Data Bus 50 60 ns Mode (Note 2) Write Timing (3.0 V ± 10%) Microcontroller Interface – AC/DC Parameters (ZPSD5XXV Versions) |
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