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ST10F168 数据表(PDF) 40 Page - STMicroelectronics

部件名 ST10F168
功能描述  16-BIT MCU WITH 256K BYTE FLASH MEMORY AND 8K BYTE RAM
PDF  74 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST10F168 数据表(HTML) 40 Page - STMicroelectronics

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The simplest way to reset the ST10F168 is to
insert a capacitor C1 between RSTIN pin and VSS,
and a capacitor between VPP pin and VSS (C0)
with a pullup resistor R0 between VPP pin and
VCC. The input RSTIN provides an internal pullup
device equalling a resistor of 50k
Ω to 150kΩ (the
minimum reset time must be determined by the
lowest value). Select C1 that produce a sufficient
discharge time to permit the internal or external
oscillator and / or internal PLL to stabilize.
To insure correct power-up reset with controlled
supply current consumption, specially if clock sig-
nal requires a long period of time to stabilized, an
asynchronous hardware reset is required during
power-up. It is recommended to connect the exter-
nal R0C0 circuit shown in Figure 12 to the VPP
pin. On power-up, the logical low level on VPP pin
forces an asynchronous harware reset when
RSTIN is asserted.
The external pullup R0 will then charge the capac-
itor C0. Note that an internal pulldown device on
VPP pin is turned on when RSTIN pin is low, and
causes the external capacitor (C0) to begin dis-
charging at a typical rate of 100
µA to 200µA. With
this mechanism, after power-up reset, short low
pulses applied on RSTIN produce synchronous
hardware reset. If RSTIN is asserted longer than
the time needed for C0 to be discharged by the
internal pulldown device, then the device is forced
in an asynchronous reset. This mechanism
insures recovery from very catastrophic failure.
Figure 12 : Minimum External Reset Circuitry
RSTOUT
VPP
RSTIN
C1
a) Hardware
VCC
+
C0
R0
ST10F168
b) For Power-up
(and Interruptible
Power-down
External Hardware
Reset
mode)
Reset
+
Figure 13 : Internal (simplified) Reset Circuitry
RSTOUT
EINIT Instruction
Trigger
Clr
Clock
Reset State
Machine
Internal
Reset
Signal
Reset Sequence
(512 CPU Clock Cycles)
SRST instruction
watchdog overflow
RSTIN
VCC
BDRSTEN
VCC
VPP (Flash device)
VPP
Weak Pulldown
(~200
µA)
From/to Exit
Powerdown
Circuit
Asynchronous
Reset
Clr
Q
Set



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