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DA9180.004

15 September, 2005

MAS9180 PAD LAYOUT

PDN

AON

RFIM

RFIP

DEC

VSS

AGC

QI

VDD

QOP

OUT

1474 µµµµm

QOM

MAS9180Ax,

x = 1..5 differential input,

B..F asymmetric input

DIE size = 1.47 x 1.46 mm; PAD size = 80 x 80

µm

Note: Because the substrate of the die is internally connected to VDD, the die has to be connected to VDD or left

floating. Please make sure that VDD is the first pad to be bonded. Pick-and-place and all component assembly

are recommended to be performed in ESD protected area.

Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die.

Pad Identification

Name

X-coordinate

Y-coordinate

Note

Power Supply Voltage

VDD

174

µm

1262

µm

Positive Quartz Filter Output for Crystal

QOP

174

µm

1057

µm

Negative Quartz Filter Output for Crystal

QOM

174

µm

854

µm

4

Quartz Filter Input for Crystal and External

Compensation Capacitor

QI

174

µm

648

µm

AGC Capacitor

AGC

174

µm

444

µm

Receiver Output

OUT

175

µm

240

µm

1

Demodulator Capacitor

DEC

1295

µm

225

µm

AGC On Control

AON

1295

µm

425

µm

2

Power Down

PDN

1295

µm

624

µm

3

Positive Receiver Input

RFIP

1295

µm

825

µm

5

Negative Receiver Input

RFIM

1295

µm

1039

µm

5

Power Supply Ground

VSS

1282

µm

1200

µm

Notes:

1) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)

-

-

at power down the output is pulled to VSS (pull down switch)

2) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)

-

Internal pull-up with current < 1

µA which is switched off at power down

3) PDN = VSS means receiver on; PDN = VDD means receiver off

Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up

(PDN=VSS) i.e. at the falling edge of PDN signal.

4) External crystal compensation capacitor pin QOM is connected only in MAS9190A5 and AF versions. It is left

unconnected in MAS9180A1 and AB..E versions which have internal compensation capacitor.

5) Differential input versions A1..A5 have 600 k

Ω biasing MOSFET-transistors towards ground from both

receiver inputs RFIP and RFIM. Asymmetric input versions AB..AF have input pin RFIM unconnected.