M58LW032D datasheet(5/50 Pages) STMICROELECTRONICS

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M58LW032D

SUMMARY DESCRIPTION

The M58LW032D is a 32 Mbit (4Mb x 8 or 2Mb

x16) non-volatile memory that can be read, erased

and reprogrammed. These operations can be per-

formed using a single low voltage (2.7V to 3.6V)

core supply.

The memory is divided into 32 blocks of 1Mbit that

can be erased independently so it is possible to

preserve valid data while old data is erased. Pro-

gram and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller simplifies the process of

programming or erasing the memory by taking

care of all of the special operations that are re-

quired to update the memory contents. The end of

a Program or Erase operation can be detected and

any error conditions identified in the Status Regis-

ter. The command set required to control the

memory is consistent with JEDEC standards.

The Write Buffer allows the microprocessor to pro-

gram from 1 to 16 Words in parallel, both speeding

up the programming and freeing up the micropro-

cessor to perform other work. A Word Program

command is available to program a single word.

Erase can be suspended in order to perform either

Read or Program in any other block and then re-

sumed. Program can be suspended to Read data

in any other block and then resumed. Each block

can be programmed and erased over 100,000 cy-

cles.

The M58LW032D has several security features to

increase data protection.

Block Protection, where each block can be

individually protected against program or

erase operations. All blocks are protected

during power-up. The protection of the blocks

is non-volatile; after power-up the protection

status of each block is restored to the state

when power was last removed.

Program Erase Enable input VPEN, program or

erase operations are not possible when the

Program Erase Enable input VPEN is low.

128 bit Protection Register, divided into two 64

bit segments: the first contains a unique

device number written by ST, the second is

user programmable. The user programmable

segment can be protected.

The Reset/Power-Down pin is used to apply a

Hardware Reset to the enabled memory and to set

the device in power-down mode.

The device features an Auto Low Power mode. If

the bus becomes inactive during read operations,

the device automatically enters Auto Low Power

mode. In this mode the power consumption is re-

duced to the Auto Low Power supply current.

The STS signal is an open drain output that can be

used to identify the Program/Erase Controller sta-

tus. It can be configured in two modes: Ready/

Busy mode where a static signal indicates the sta-

tus of the P/E.C, and Status mode where a pulsing

signal indicates the end of a Program or Block

Erase operation. In Status mode it can be used as

a system interrupt signal, useful for saving CPU

time.

The memory is available in TSOP56 (14 x 20 mm)

and TBGA64 (10x13mm, 1mm pitch) packages.

In addition to the standard version, the packages

are also available in Lead-free version, in compli-

ance with JEDEC Std J-STD-020B, the ST ECO-

PACK 7191395 Specification, and the RoHS

(Restriction of Hazardous Substances) directive.

All packages are compliant with Lead-free solder-

ing processes.

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