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ST10R172L 数据表(PDF) 60 Page - STMicroelectronics |
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ST10R172L 数据表(HTML) 60 Page - STMicroelectronics |
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60 / 68 page ![]() 60/68 ST10R172L - ELECTRICAL CHARACTERISTICS 15.3.6 External Bus Arbitration VDD = 3.3 V ± 0.3 V VSS = 0 V TA = -40°C to +85 °C CL = 50 pF Parameter Symbol Max. CPU Clock = 50 MHz Variable CPU Clock 1/2TCL = 1 to 50 MHz min. max. min. max. HOLD input setup time to CLKOUT t61 SR 15 – 15 – ns CLKOUT to HLDA high or BREQ low delay t62 CC – 10 – 10 ns CLKOUT to HLDA low or BREQ high delay t63 CC – 10 – 10 ns CSx release t64 CC – 15 – 15 ns CSx drive t65 CC -3 15 -3 15 ns Other signals release t66 CC – 15 – 15 ns Other signals drive t67 CC -3 15 -3 15 ns Table 17 External bus arbitration 1 |
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