Detailed description

VL6522

14/35

4.3.2

If 'manual_mode' is set, then the SCL/SDA lines can be bit bashed by writing direct to 'sda'

and 'scl'. Otherwise these are controlled automatically. The 'clk_div' reg is used to slow

down the clock if necessary (default is zero which should result in approx 400 kHz SCL).

The 'start' bit will generate an I2C start bus condition when set high.

The 'cmd_processed' bit will initially be set low and then go high when the command is

complete.

will initially be set low and then go high when the command is complete.

The 'read' bit will kick off a read from the current address. The 'cmd_processed' bit will be

set low and then go high when the command is complete. At this point the READ_BYTE

register will contain the data.

If the 'multiple_read' bit is set, then the address will be auto-incremented after each 'read'.

That is, you can kick off another read without first having to set the address.

To write a byte, write the data value into the WRITE_BYTE register, then wait for the

'cmd_processed' bit to go high. Finally check that the 'ack_rx' (acknowledge recieved) bit is

high.

The 'eeprom_present' bit is set by the firmware when it first attempts to address the eeprom.

If it gets an acknowledge then this bit is set high, otherwise it is set low.

Note:

See Table 10 on page 17 for locations of and information on relevant registers.