87993AYI

www.icst.com/products/hiperclocks.html

REV. B May 21, 2003

9

Integrated

Circuit

Systems, Inc.

ICS87993I

Figure 5A shows a schematic example of the ICS87993I. In this

example, the CLK0/nCLK0 input is selected as primary. The in-

put is driven by an LVPECL driver. Feedback can be either from

Bank A or Bank B depending on the application. The decoupling

capacitors should be physically located near the power pin.

For ICS87993I, the unused outputs can be left floating.

Zo = 50 Ohm

C3

0.1uF

R3

50

U1

ICS87993I

1

2

3

4

5

6

7

8

17

18

19

20

21

22

23

24

nMR

nALM_RS

CLK0

nCLK0

CLK_SEL

CLK1

nCLK1

VEE

VCC

nQB2

QB2

nQB1

QB1

nQB0

QB0

VCC

R13

50

C1

0.1uF

VCC

R16

1K

R6

50

R10

50

(U1-29)

C11

0.01u

VCC

VCC

R1

50

+

-

Zo = 50

LVCMOS

Zo = 50

CLK_SEL

R11

50

VCC

C7 (Option)

0.1u

Zo = 50 Ohm

VCC

C5 (Option)

0.1u

C2

0.1uF

Zo = 50 Ohm

Zo = 50 Ohm

VCC

R9

50

C8 (Option)

0.1u

LVPECL Driv er

R2

50

VCC

(U1-24)

R12

50

(U1-17)

(U1-16)

C4

0.1uF

C6 (Option)

0.1u

LVCMOS

R5

50

LVCMOS

R7

10

LVPECL Driv er

VCCA

LVCMOS

R15

1K

R14

50

R4

50

C16

10u

R2

1K