87993AYI

www.icst.com/products/hiperclocks.html

REV. B May 21, 2003

1

Integrated

Circuit

Systems, Inc.

ICS87993I

The ICS87993I is a PLL clock driver designed

specifically for redundant clock tree designs. The

device receives two differential LVPECL clock

signals from which it generates 5 new differen-

tial LVPECL clock outputs. Two of the output pairs

regenerate the input signal frequency and phase while the

other three pairs generate 2x, phase aligned clock outputs.

External PLL feedback is used to also provide zero delay

buffer performance.

The ICS87993I Dynamic Clock Switch (DCS) circuit continu-

ously monitors both input CLK signals. Upon detection of a

failure (CLK stuck HIGH or LOW for at least 1 period), the

INP_BAD for that CLK will be latched (H). If that CLK is the

primary clock, the DCS will switch to the good secondary

clock and phase/frequency alignment will occur with minimal

output phase disturbance. The typical phase bump caused

by a failed clock is eliminated.

HiPerClockS™

,&6

• 5 differential 3.3V LVPECL outputs

• Selectable differential clock inputs

• CLKx, nCLKx pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

• VCO range: 200MHz to 500MHz

• External feedback for “zero delay” clock regeneration

with configurable frequencies

• Cycle-to-cycle jitter (RMS): 20ps (maximum)

• Output skew: 70ps (maximum), within one bank

• 3.3V supply voltage

• -40°C to 85°C ambient operating temperature

• Pin compatible with MPC993

32-Lead QFP (LQFP)

7mm x 7mm x 1.4mm

package body

Y Package

Top View

24 23 22 21 20 19 18 17

1

2

3

4

5

6

7

8

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

INP0BAD

INP1BAD

CLK_SELECTED

nEXT_FB

EXT_FB

nQA1

QA1

nQA0

QA0

MAN_OVERRIDE

PLL_SEL

ICS87993I

PLL

÷2

÷4

Dynamic Switch

Logic

nQB0

QB0

nQB1

QB1

nQB2

QB2

nQA0

QA0

nQA1

QA1

PLL_SEL

CLK_SELECTED

INP1BAD

INP0BAD

MAN_OVERRIDE

ALARM_RESET

SEL_CLK

nCLK0

CLK0

nCLK1

CLK1

nEXT_FB

EXT_FB

nMR