ST5090AD datasheet(14/29 Pages) STMICROELECTRONICS

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Transmit/Receive enabling/disabling

Bit ’EN’ (2) enables or disables voice data trans-

fer on DX and DR pins. When disabled, PCM data

from DR is not decoded and PCM time-slots are

high impedance on DX. Default value is disabled.

B-channel selection (1)

Bit TS(1) permits selection between B1 or B2

channels. Default value is B1 channel.

Supply Voltage selection

Bit SV (0) permits selection of the power supply of

the ST5090. Default value is 3.3V.

CONTROL REGISTER CR2 (1)

Data sent to receive path or data received from

DR input. Refer to bit MR(4) in ”Control Register

CR1” paragraph.

CONTROL REGISTER CR3 (1)

DX data transmitted. Refer to bit MX(3) in ”Control

CONTROL REGISTER CR4

First byte of a READ or a WRITE instruction to

Control Register CR4 is as shown in TABLE 1.

Second byte is as shown in TABLE 6.

Transmit Input Selection

MIC1 or MIC2 or MIC3 or transmit mute can be

selected with bits 6 and 7 (VS and TE).

Transmit gain can be adjusted within a 22.5 dB

range in 1.5 dB step with Register CR5.

Sidetone Selection

Bit ”SI” (5) enables or disables Sidetone circuitry.

When enabled, sidetone gain can be adjusted

with Register (CR5). When Transmit path is dis-

abled, sidetone circuit is also disabled.

Output Driver Selection

Bits OE1(4) and OE2(3) provide the selection

among the earpiece output or the extra amplifier

output or both outputs muted.

OE1 = 1 and OE2 = 1 is not allowed.

Ring/Tone signal selection

Bit RTE (2) provide select capability to connect

on-chip Ring/Tone generator either to an extra

amplifier input or to earpiece amplifier input.

PCM receive data selection

Bits ”SE” (0) provide select capability to connect

received speech signal either to an extra amplifier

input or to earpiece amplifier input.

CONTROL REGISTER CR5

First byte of a READ or a WRITE instuction to

Control Register CR5 is as shown in TABLE 1.

Second byte is as shown in TABLE 7.

Transmit gain selection

Transmit amplifier can be programmed for a gain

from 0dB to 22.5dB in 1.5dB step with bits 4 to 7.

0 dBmO level at the output of the transmit ampli-

fier (A reference point) is 0.492 Vrms (overload

voltage is 0.707 Vrms).

Sidetone attenuation selection

Transmit signal picked up after the switched ca-

pacitor low pass filter may be fed back into both

Receive amplifiers.

Attenu ation of the signal at the output of the

sidetone attenuator can be programmed from

–12.5dB to -27.5dB relative to reference point

A in 1 dB ste p with bits 0 to 3.

CONTROL REGISTER CR6

First byte of a READ or a WRITE instruction to

Control Register CR6 is as shown in TABLE 1.

Second byte is as shown in TABLE 8.

Earpiece amplifier gain selection:

Earpiece Receive gain can be programmed in 2

dB step from 0 dB to -30 dB relative to the maxi-

mum with bits 4 to 7.

0 dBmO voltage at the output of the amplifier on

pins VFr+ and VFr- is then 1.965 Vrms when 0dB

gain is selected down to 61.85 Vrms when -30dB

gain is selected.

Extra amplifier gain selection:

Extra Receive amplifier gain can be programmed

in 2 dB step from 0 dB to -30 dB relative to the

maximum with bits 0 to 3.

0 dBmO voltage on the output of the amplifier on

pins VLr+ and VLr- 1.965 Vrms when 0 dB gain is

selected down to 61.85 mVrms when -30 dB gain

is selected.

CONTROL REGISTER CR7:

First byte of a READ or a WRITE instruction to

Control Register CR7 is as shown in TABLE 1.

Second byte is as shown in TABLE 9.

(1) Significant in companded mode only

ST5090

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