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ST5090AD 数据表(PDF) 19 Page - STMicroelectronics |
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ST5090AD 数据表(HTML) 19 Page - STMicroelectronics |
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19 / 29 page  TIMING SPECIFICATIONS (unless otherwise specified, VCC = 3.3V + 10%or 5V ± 10%, TA =–30°Cto85°C; typical characteristics are specified VCC = 3.3V, TA =25 °C; all signals are referenced to GND, see Note 5 for timing definitions) NOTICE: All timing specifications can be changed. MASTER CLOCK TIMING Symbol Parameter Test Condition Min. Typ. Max. Unit fMCLK Frequency of MCLK Selection of frequency is programmable (see table 2) 512 1.536 2.048 2.560 kHz MHz MHz MHz tWMH Period of MCLK high Measured from VIH to VIH 80 ns tWML Period of MCLK low Measured from VIL to VIL 80 ns tRM Rise Time of MCLK Measured from VIL to VIH 30 ns tFM Fall Time of MCLK Measured from VIH to VIL 30 ns PCM INTERFACE TIMING Symbol Parameter Test Condition Min. Typ. Max. Unit tHMF Hold Time MCLK low to FS low 0 ns tSFM Setup Time, FS high to MCLK low 30 ns tDMD Delay Time, MCLK high to data valid Load = 100 pf 100 ns tDMZ Delay Time, MCLK low to DX disabled 10 100 ns tDFD Delay Time, FS high to data valid Load = 100 pf ; Applies only if FS rises later than MCLK rising edge in Non Delayed Mode only 100 ns tSDM Setup Time, DR valid to MCLK receive edge 20 ns tHMD Hold Time, MCLK low to DR invalid 10 ns tHMFR Hold Time MCLK High to FS low 30 ns tSFMR Setup Time, FS high to MCLK High 30 ns tDMDR Delay Time, MCLK low to data valid Load = 100pF 100 ns tDMZR Delay Time, MCLK High to DX disabled 10 100 ns tHMDR Hold Time, MCLK High to DR invalid 20 ns ABSOLUTE MAXIMUM RATINGS Parameter Value Unit VCC to GND 7V Voltage at MIC (VCC ≤ 5.5V) VCC +1 to GND -1 V Current at VFr and VLr + 100 mA Current at any digital output + 50 mA Voltage at any digital input (VCC ≤ 5.5V); limited at + 50mA VCC + 1 to GND - 1 V Storage temperature range - 65 to + 150 °C Lead Temperature (wave soldering, 10s) + 260 °C ST5090 19/29 |
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