ST52T410 datasheet(29/84 Pages) STMICROELECTRONICS

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ST52T410/ST52T420/E420

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Routine associated to the interrupt with higher

priority will start.

In order to avoid possible conflicts between

interrupt masking set in the main program, or

inside high level language compiler macros, the

GIP is hung up through the User Global Interrupt

Mask or the Macro Global Interrupt Mask (see

Figure 4.2).

UEGI/UDGI instruction switches on/off the User

Global Interrupt Mask, enabling/disabling the GIR

for the main program.

MEGI/MDGI instructions switch the Macro Global

Interrupt Mask on/off, in order to ensure that the

macro will not be broken.

4.3 Interrupt Sources

ST52T410/ST52x420 manages interrupt signals

generated by the internal peripherals (PWM/

Timers and Analog to Digital Converter) or coming

from the INT/PC0 pin. The External Interrupt is

active on the rising of INT/PC0 signal.

Each peripheral can be programmed in order to

generate the associated interrupt; further details

are described in the related chapter.

4.4 Interrupt Maskability

The interrupts can be masked by configuring the

REG_CONF 0 by means of LDCR, or LDCE,

instruction. The interrupt is enabled when the bit

associated to the mask interrupt is “1". Viceversa,

when the bit is ”0", the interrupt is masked and is

kept pendent.

For example:

LDRC 10,6 //load the constant 6 in the

RAM Register 10

LDCR 0, 10 // set the CONF_REG 0 with

the value stored in the RAM Register

the result is CONF_REG0 =00000110 enabling the

interrupts deriving from the ADC (INT_ADC)

(ST52x420 only) and from the PWM/TIMER 0

(INT_PWM/TIMER0).

(*) ST52x420 only

Reset Configuration ‘000000’

Table 4.1 Configuration Register 0

Description

Bit

Name

Value

Description

0MSKE

External Interrupt

Masked

External Interrupt

Not Masked

MSKAD

A/D Converter (*)

Interrupt

Masked

A/D Converter (*)

Interrupt

Not Masked

MSKTM0

PWM/TIMER 0

Interrupt

Masked

PWM/TIMER 0

Interrupt

Not Masked

MSKTM1

PWM/TIMER 1

Interrupt

Masked

PWM/TIMER 1

Interrupt

Not Masked

MSKTM2

PWM/TIMER 2

Interrupt

Masked

PWM/TIMER 2

Interrupt

Not Masked

Not used

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