ST52T410 datasheet(31/84 Pages) STMICROELECTRONICS

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ST52T410/ST52T420/E420

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Figure 4.5 Interrupt Configuration Register 1

4.5 Interrupt Priority

Six priority levels are available: level 5 has the

lowest priority, level 0 has the highest priority.

Level 5 is associated to the Main Program, levels 4

to 1 are programmable by means of the priority

registers called REG_CONF1 (see Figure 4.5 and

Table 4.3); whereas the higher level is related to

the external interrupt (INT_EXT).

PWM/Timers and ADC are identified by a two-bit

Peripheral Codes (see Table 4.2); in order to set

the

i-th priority level the user must write the

peripheral label

i in the related INTi priority level.

i.e.

LDRC

10,

201

//(load

the

value

201=’11001001’ in the RAM Register 10)

LDCR

set

the

REG_CONF1=

‘11001001’

The following priority levels are defined:

Level 1: INT_PWM/TIMER0 (PWM/TIMER 0

Code: 01)

Level 2: INT_PWM/TIMER0 (PWM/TIMER 1

Code: 10)

Level 3: INT_ADC (ADC Code: 00) (ST52x420

only)

Level 4: INT_PWM/TIMER0 (PWM/TIMER 2

Code: 11)

Table 4.3 Conf. Register 1

Bit

Name

Value

Level

0, 1

INT1

Peripheral

Code

High

2,3

INT2

Peripheral

Code

Medium-High

4,5

INT3

Peripheral

Code

Medium-Low

REG_CONF 1

PRIORITY HIGH

PRIORITY MED. HIGH

PRIORITY MED. LOW

PRIORITY LOW

LOW

MEDL

MEDH

HIGH

MEDH

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