PSD413A1 datasheet(13/123 Pages) STMICROELECTRONICS

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PSD4XX Family

9.0

The PSD4XX

Architecture

PSD4XX consists of five major functional blocks:

t ZPLD Blocks

t Bus Interface

t I/O Ports

t Memory Block

t Power Management Unit

The functions of each block are described in the following sections. Many of the blocks

perform multiple functions, and are user configurable. The chip configurations are specified

by the user in the PSDsoft Development Software. Other configurations are specified by

setting up the appropriate bits in the configuration registers during run time.

9.1 The ZPLD Block

The PSD4XX series devices provide two ZPLD configurations. The ZPLD in the

PSD4XXA1 devices has 8 registered macrocells, 8 combinatorial macrocells, and up to 113

product terms.

The PSD4XXA2 has a full function ZPLD with 24 registered macrocells and up to 126

product terms.

9.1.1 The PSD4XXA1 ZPLD Block

Key Features

t 2 Embedded ZPLD devices

t 8 registered and 8 combinatorial macrocells

t Combinatorial/registered outputs

t Maximum 113 product terms

t Programmable output polarity

t User configured register clear/preset

t User configured register clock input

t 37 Inputs

t Accessible via 16 I/O pins

t Power Saving Mode

t UV-Erasable

General Description

The ZPLD block has 2 embedded PLD devices:

t DPLD

The Address Decoding PLD, generating select signals to internal I/O or memory blocks.

t GPLD

The General Purpose PLD provides 8 registered and combinatorial programmable

macrocells for general or complex logic implementation; dedicated to user application.

Figure 4 shows the architecture of the ZPLD. The PLD devices all share the same input

bus. The true or complement of the 37 input signals are fed to the programmable

AND-ARRAY. Names and sources of the input signals are shown in Table 3. The PB

signals, depending on user configuration, can either be macrocell feedbacks or inputs from

Port B.

PSD413A1 数据表(PDF) 13 Page - STMicroelectronics

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