PSD413A1 datasheet(29/123 Pages) STMICROELECTRONICS

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PSD4XX Family

The PSD4XX

Architecture

(cont.)

9.1.2.2 The GPLD

The structure of the General Purpose PLD consists of a programmable AND ARRAY and

3 sets of I/O Macrocells. The ARRAY has 59 input signals, same as the DPLD. From these

inputs, “ANDed” functions are generated as product term inputs to the macrocells. The I/O

Macrocell sets are named after the I/O Ports they are linked to, e.g., the macrocells

connected to Port A are named PA Macrocells. The 3 sets of macrocells, PA, PB and PE,

are similar in structure and function.

Figure 13 shows the output/input path of a GPLD macrocell to the Port pin with which it is

associated. If the Port pin is specified as a GPLD output pin in PSDsoft, the MUX in the I/O

Port Cell selects the GPLD macrocell as an output of the Port pin. The output enable signal

to the buffer in the I/O cell can be controlled by a product term from the AND ARRAY.

If the Port pin is specified as a ZPLD input pin, the MUX in the GPLD macrocell selects the

Port input signal to be one of the 61 signals in the ZPLD Input Bus.

9.1.2.3 Port A Macrocell Structure

Figure 14 shows the PA Macrocell block, which consists of 8 identical macrocells.

Each macrocell output can be connected to its own I/O pin on Port A. There are 3 user

programmable global product terms output from the GPLD’s AND ARRAY which are

shared by all the macrocells in Port A:

t PA.OE

Enable or tri-state Port A output pins

t PA.PR

Preset D flip flop in the macrocells

t PA.RE

Reset/Clear D flip flop in the macrocells

Two other inputs, CLKIN and MACRO-RST, are used as clock and clear inputs to the D flip

flop. The CLKIN comes directly from the CLKIN input pin. The MACRO-RST is the same as

the Reset input pin except it is user configurable.

The circuit of a PA Macrocell is shown in Figure 15. There are 6 product terms from the

GPLD’s AND ARRAY as inputs to the macrocell. Users can select the polarity of the

output, and configure the macrocell to operate as:

t Registered Output

Select output from D flip flop

t Combinatorial Output

Select output from OR gate

t GPLD Input

Use Port A pin as dedicated input

t GPLD Output

Use Port A pin as dedicated output

t GPLD I/O

Use Port A pin as bidirectional pin

t Macrocell Feedback

the combinatorial output, to expand the number of product terms available to another

macrocell.

In case of "Buried Feedback", where the output of the macrocell is not connected to a

Port A pin, Port A can be configured to perform other user defined I/O functions.

The two global product terms assigned for asynchronous clear (PA.RE) and preset (PA.PR)

are mainly for proper PA Macrocell initialization. The macrocell flip-flop can also be cleared

during reset by MACRO-RST, if such an option is chosen. The clock source is always the

input clock CLKIN.

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