ST5451 datasheet(16/34 Pages) STMICROELECTRONICS

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4 - 7 - DMA ACCESS

The HDLC controller has a DMA interface which

is activated by DMA bit in MODE register.The

DMA interface is available only when multiplexed

bus is selected.

ST 5451 asserts DMA REQR or DMA REQX to

request an exchange of bytes between the FIFOS

and the external memory.

The external DMA controller asserts DMA ACKR

or DMA ACKX to access the FIFOS.

These signals are equivalent to E/DS/RD func-

tions.

During DMA access, CS/CE pin must be inactive;

AS and E/DS/RD signals can be present.

Outside DMA Access, all registers are accessible

by the

µP except the FIFOS.

FRAME RECEPTION:

When one block has been stored in RFIFO, DMA

REQ R pin goes low and RPF (or RME) interrupts

the

µP. The DMA controller reads the RFIFO. Af-

ter the RME interrupt, the frame length will be

available in RFBC register. The block is acknow-

ledged by RMC command.

FRAME TRANSMISSION:

When a 32 byte block is free in XFIFO, DMA re-

quest goes low and XPR interrupts the

µP. The

DMA controller can write data in the XFIFO. At

the end of the frame, the

µP send XME to HDLC

controller; CRC and closing flag will be sent by

the HDLC controller.

Figure 5: D and C/I channels Access Procedure

ST5451

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