ST5451 datasheet(17/34 Pages) STMICROELECTRONICS

17 / 34 page

4 - 8 - INTERRUPT PROCEDURE

4 - 8 - 1 - HDLC CHANNELS

4 - 8 - 1 - 1 - RECEIVE DIRECTION

RRE and RPF interrupts

RPF bit (register ISTA0) set high to indicate the

HDLC controller has received a block of 32 bytes

which is not a complete message.

This bit remains high until it is erased by the mi-

croprocessor.

As for each bit of ISTA0 register, except the ex-

tension bits of ISTA1 and ISTA2 (EXI1, EXI2), the

way to erase RPF is to write a ”0” at its location

and to write a ”1” at the location of the others (for

example 7FH into ISTA0 to erase RME). The

processing order is:

- put Mask0 on ISTA0 (if Mask Off)

- (Read FIFOR) X 32

- Write ISTA0 to erase RPF (BFH)

- Write RMC to ”1” for asking for another block

of the frame

(NB: RMC, RMD are automatically erased

by the controller)

- Remove Mask0

RME bit (register ISTA0) set high to indicate the

HDLC controller has received a short frame or the

last block of a large frame. The message is now

complete, the bit remains high until it is erased by

the microprocessor. The processing order is:

- put Mask0 on ISTA0 (if upper level Mask Off)

- Read RFBC with a mask on the 3 most sig-

nificant bits, to know the number ”N” of

transfers to do

- (Read FIFOR) x N for data

- Read FIFOR for status on the frame

- Write ISTA0 to erase RME (7FH)

- Write RMC or RMD to ”1” for asking for an-

other frame.

RF0 interrupts

RF0 is a bit of the interrupt register ISTA0 set

high to indicate an overflow of the receive FIFO

has been detected, either because more than 8

frames cannot be stored or because more than

64 bytes can’t be stored. This information is also

stored into the status of the concerned frame

(RDO).

The processing order of the microprocessor is:

- Looking for RPF and RME bits and pop - up

the frames. Then look for the status and

throw down the frame concerned. In general

case, only one frame is lost.

4 - 8 - 1 - 2 - TRANSMIT DIRECTION

XPR Interrupt

XPR is a bit of the interrupt register ISTA0 coming

high to indicate HDLC controller has a free block

of 32 bytes. This bit remains high until the micro-

processor write a byte into the block and erase

this bit into ISTA0; if another block is free, XPR

get high again immediately.

The processing order of the microprocessor is in

non DMA Mode:

- Put Mask0 on ISTA0 (if upper level Mask Off)

- Write at least one byte into FIFOX

- Write ISTA0 to erase XPR

- Write XHF to ”1” for launching the transmit

operation of block (a block is not necessarily

32 bytes)

or write XME to ”1” for launching the trans-

mit of a short frame or of the last part of a

frame

- Remove masks

In DMA Mode two general cases are possible:

1) The external DMA controller works by ”pages”

less or equal to 32 bytes. The ”process” of the

DMAC is a short frame transmission and the

processor must give an XME at the end of the

DMAC process (refer to figure 2).

2) The DMA controller works by ”pages” of more

than 32 bytes. It’s process is the transfer of the

whole frame.

The circuit doesn’t need an XHF at the end of an

intermediate 32 byte block; since it has reached

32 bytes written into the current fifo, it begins the

transfer and toggles on the second fifo as soon as

the first is full. (At this moment an XME is possi-

ble if the 32

nd byte was the end of the frame -

case 1) and then, a 33

rd write operation into the

fifo generates an internal XHF and the frame fol-

lowing blocks are expected.

- In the two cases the flow control is done be-

tween DMAC and ST5451 by the way of

REQX and ACKX signals

The processing order is:

- Put Mask0

- Give order to DMAC to begin transfer

- Wait for DMAC end of process

- Write ISTA to erase on XPR

- Write XME to signal the end of the frame to

the ST5451 (otherwise the ST5451 will put

”underrun” interrupt, as soon as its two

blocks are free).

XDU Interrupt

XDU is a bit of the interrupt register ISTA0 com-

ing high to indicate HDLC controller has detected

an underrun (a frame is being transmitted and no

more bytes are available into the FIFO).

The HDLC controller finish the frame by transmit-

ting an ”Abort” and no more data can be transmit-

ted even in NHF mode. To be sure XDU is seen

by the MIcroprocessor, XDU interrupt bit must be

erased in ISTA0 in addition of XRES security pro-

cedure

The transmit control is frozen and the only way to

reinitialize a transmit session is to write an XRES,

after erasing XDU.

ST5451

17/34

ST5451 数据表(PDF) 17 Page - STMicroelectronics

ST5451 数据表(HTML) 17 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

数据表下载