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ST5451D 数据表(PDF) 25 Page - STMicroelectronics

部件名 ST5451D
功能描述  ISDN HDLC AND GCI CONTROLLER
PDF  34 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST5451D 数据表(HTML) 25 Page - STMicroelectronics

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ELECTRICAL CHARACTERISTICS (T from 0 to 70
°C, VDD =5 ± 0.25V).
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
IS
Supply Current
CLK Freq. = 4MHz
CLK Freq. = 2MHz
NO CLK Freq.
–
–
–
4
2
20
–
4
300
mA
mA
µA
STATIC CHARACTERISTICS - GCI INTERFACE (T from 0 to 70
°C, VDD =5 ± 0.25V).
Symbol
Parameter
Condition
Min.
Max.
Unit
VIH
High Level Input Voltage
Maximum leakage current :
± 10
µA
2.4
VDD+0,4
V
VIL
Low Level Input Voltage
Maximum leakage current :
± 10
µA
VSS-0,4
0,8
V
VOH
High Level Output Voltage
IOH = -0,4
µA
2,4
V
VOL
Low Level Output Voltage
IOL = 2mA
0,45
V
VOL
Low Level Output Voltage
DOUT .Din . INT
IOL = 7mA
0,45
V
C
Input/Output Capacity
10
pF
COUT
Load Capacity DIN/DOUT
150
pF
Load Capacity INT
150
pF
Load Capacity AD0/7
100
pF
DYNAMIC ELECTRICAL CHARACTERISTICS - GCI Interface
Symbol
Parameter
Min.
Typ.
Max.
Unit
FSync
8 KHz
8
KHz
FCLK
64 x n x FSync 1
≤ n ≤ 8
512
4096
KHz
tWCH
Period of CLK High
80
ns
tWCL
Period of CLK Low
80
ns
tRC
Rise Time of CLK
10
ns
tFC
Full Time of CLK
10
ns
tHCF
Hold Time: CLK - FS
0
ns
tSFC
Set-up Time: FS - CLK
30
ns
tDCD
Delay Time: CLK High to data valid. out: 150 pF
80
ns
tDCZ
Delay Time: to Data Disabled
0
80
ns
tDFD
Delay Time: FSync. High to data valid. count: 150 pF. Applies
only if Sync rises later than CLK raising edge.
80
ns
tSDC
Set-up Time: Data valid to CLK receive edge.
30
ns
tHDC
Hold Time: CLK low to data invalid.
30
ns
ST5451
25/34



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