ST6215 datasheet(32/105 Pages) STMICROELECTRONICS

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ST6215C/ST6225C

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6.7 REGISTER DESCRIPTION

INTERRUPT OPTION REGISTER (IOR)

Address: 0C8h

—

Write Only

Reset status: 00h

Caution: This register is write-only and cannot be

accessed by single-bit operations (SET, RES,

DEC,...).

Bit 7 =Reserved, must be cleared.

Bit 6 = LES

Level/Edge Selection bit.

0: Falling edge sensitive mode is selected for inter-

rupt vector #1

1: Low level sensitive mode is selected for inter-

rupt vector #1

Bit 5 = ESB

Edge Selection bit.

0: Falling edge mode on interrupt vector #2

1: Rising edge mode on interrupt vector #2

Bit 4 = GEN

Global Enable Interrupt.

0: Disable all maskable interrupts

1: Enable all maskable interrupts

Note: When the GEN bit is cleared, the NMI inter-

rupt is active but cannot be used to exit from STOP

or WAIT modes.

Bits 3:0 = Reserved, must be cleared.

Table 7. Interrupt Mapping

LES

ESB

GEN

Vector

number

Source

Block

Description

Label

Flag

Exit

from

STOP

Vector

Address

Priority

Order

RESET

Reset

N/A

yes

FFEh-FFFh

Vector #0

NMI

Non Maskable Interrupt

N/A

yes

FFCh-FFDh

NOT USED

FFAh-FFBh

FF8h-FF9h

Vector #1

Port A

Ext. Interrupt Port A

N/A

yes

FF6h-FF7h

Vector #2

Port B, C

Ext. Interrupt Port B, C

N/A

yes

FF4h-FF5h

Vector #3

TIMER

Timer underflow

TSCR

TMZ

yes

FF2h-FF3h

Vector #4

ADC

End Of Conversion

ADCR

EOC

FF0h-FF1h

Priority

Lowest

Highest

Priority

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