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ST62T18C 数据表(PDF) 31 Page - STMicroelectronics |
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ST62T18C 数据表(HTML) 31 Page - STMicroelectronics |
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31 / 82 page ![]() 31/82 ST62T18C/E18C INTERRUPTS (Cont’d) Interrupt Polarity Register (IPR) Address: DAh — Read/Write In conjunction with I/O register ESB bit, the polarity of I/O pins triggered interrupts can be selected by setting accordingly the Interrupt Polarity Register (IPR). If a bit in IPR is set to one the corresponding port interrupt is inverted (e.g. IPR bit 2 = A; port C generates interrupt on rising edge. At reset, IPR is cleared and all port interrupts are not inverted (e.g. Port C generates interrupts on falling edges). Bit 7 - Bit 4 = Unused. Bit 3 = Port D Interrupt Polarity. Bit 2 = Unused. Bit 1= Port A Interrupt Polarity. Bit 0 = Port B Interrupt Polarity. Tables 11. I/O Interrupts selections according to IPR, IOR programming 70 - - - - PortD - PortA PortB GEN IPR3 IPR0 IOR5 Port B occurrence Port D occurrence Interrupt source 1 0 0 0 falling edge falling edge 2 1 0 0 1 rising edge rising edge 1 0 1 0 rising edge falling edge 1 0 1 1 falling edge rising edge 1 1 0 0 falling edge rising edge 1 1 0 1 rising edge falling edge 1 1 1 0 rising edge rising edge 1 1 1 1 falling edge falling edge 0 X X X Disabled Disabled GEN IPR1 IOR6 Port A occurrence Interrupt source 1 0 0 falling edge 1 1 0 1 low level 1 1 0 rising edge 1 1 1 high level 0 X X Disabled 31 |
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