ST62T18C datasheet(55/82 Pages) STMICROELECTRONICS

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ST62T18C/E18C

U. A. R. T (Cont’d)

4.5.4 Data Reception

The UART continuously looks for a falling edge on

the input pin whenever a transmission is not ac-

tive. Once an edge is detected it waits 1 bit time (8

states) to accommodate the Start bit, and then as-

sembles the following serial data stream into the

data register. First 8 bit are stored into the UART

Data Register, while the additionnal 9th bit is

stored into the LSB of the UART Control Register

in case of the 11-bit frame MCU option has been

selected. When the 10-bit frame option is selected,

the parity of the 8 received bit is automatically writ-

ten into the LSB of the UART Control Register

(PTYEN bit).

After all bit have been received, the Receiver waits

for the duration of one bit (for the Stop bit) and

then transfers the received data into the buffer reg-

ister, allowing a following character to be received.

The interrupt flag RXRDY is set to 1 as the data is

transferred to the buffer register and, if enabled,

will generate an interrupt.

Figure 33. Data Sampling Points

If a transmission is started during the course of a

reception, the transmission takes priority and the

reception is stopped to free the resources for the

transmission. This implies that a handshaking sys-

tem must be implemented, as polling of the UART

to detect reception is not available.

4.5.5 Interrupt Capabilities

Both reception and transmission processes can in-

duce interrupt to the core as defined in the inter-

rupt section. These interrupts are enabled by set-

ting TXIEN and RXIEN bit in the UARTCR register,

and TXMT and RXRDY flags are set accordingly

to the interrupt source.

4.5.6 Registers

UART Data Register (UARTDR)

Address: D6h, Read/Write

Bit7-Bit0.

UART data bits. A write to this register

loads the data into the transmit shift register and

triggers the start of transmission. In addition this

resets the transmit interrupt flag TXMT. A read of

this register returns the data from the Receive

buffer. If the automatic even parity computation is

set (Bit PTYEN set), D7 must be cleared to 0 be-

fore transmission. Only the 7 LSB D0..D6 contain

the data to be sent.

Warning. No Read/Write Instructions may be

used with this register as both transmit and receive

share the same address

Table 19. Baudrate Selection

VR02010

1 BIT

345

SAMPLES

BR2

BR1

BR0

fINT Division

Baud Rate

fINT = 8MHz

fINT = 4MHz

6.656

1200

600

3.328

2400

1200

1.664

4800

2400

832

9600

4800

416

19200

9600

256

31200

15600

208

38400

19200

104

76800

38400

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