数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

ST6208CB3 数据表(PDF) 28 Page - STMicroelectronics

部件名 ST6208CB3
功能描述  8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, OSCILLATOR SAFEGUARD, SAFE RESET AND 20 PINS
PDF  70 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST6208CB3 数据表(HTML) 28 Page - STMicroelectronics

Back Button ST6208CB3 Datasheet HTML 24Page - STMicroelectronics ST6208CB3 Datasheet HTML 25Page - STMicroelectronics ST6208CB3 Datasheet HTML 26Page - STMicroelectronics ST6208CB3 Datasheet HTML 27Page - STMicroelectronics ST6208CB3 Datasheet HTML 28Page - STMicroelectronics ST6208CB3 Datasheet HTML 29Page - STMicroelectronics ST6208CB3 Datasheet HTML 30Page - STMicroelectronics ST6208CB3 Datasheet HTML 31Page - STMicroelectronics ST6208CB3 Datasheet HTML 32Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 28 / 70 page
background image
28/70
ST62T08C/T09C ST62T10C/T20C/E20C
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h
Write Only
Reset status: 00h
Bit 7, Bits 3-0 = Unused.
Bit 6 = LES: Level/Edge Selection bit.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Bit 5 = ESB: Edge Selection bit.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN: Global Enable Interrupt. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt Sources
Interrupt sources available on the ST62E20C/
T20C are summarized in the Table 9 with associ-
ated mask bit to enable/disable the interrupt re-
quest.
Table 9. Interrupt Requests and Mask Bits
*Except ST62T08C
70
-
LES
ESB
GEN
-
-
-
-
Peripheral
Register
Address
Register
Mask bit
Masked Interrupt Source
Interrupt
vector
GENERAL
IOR
C8h
GEN
All Interrupts, excluding
NMI
TIMER
TSCR
D4h
ETI
TMZ: TIMER Overflow
Vector 3
A/D CONVERTER(*)
ADCR
D1h
EAI
EOC: End of Conversion
Vector 4
Port PAn
ORPA-DRPA
C4h-CCh
ORPAn-DRPAn
PAn pin
Vector 1
Port PBn
ORPB-DRPB
C5h-CDh
ORPBn-DRPBn
PBn pin
Vector 2
116



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com