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ST62T52B 数据表(PDF) 19 Page - STMicroelectronics

部件名 ST62T52B
功能描述  8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER AND EEPROM
PDF  68 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST62T52B 数据表(HTML) 19 Page - STMicroelectronics

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ST62T52B ST62T62B/E62B
RESETS (Cont’d)
3.2.3 Watchdog Reset
The MCU provides a Watchdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog register is not refreshed
before an end-of-count condition is reached, the
internal reset will be activated. This, amongst oth-
er things, resets the watchdog counter.
The MCU restarts just as though the Reset had
been generated by the RESET pin, including the
built-in stabilisation delay period.
3.2.4 Application Notes
No external resistor is required between VDD and
the Reset pin, thanks to the built-in pull-up device.
The POR circuit operates dynamically, in that it
triggers MCU initialization on detecting the rising
edge of VDD. The typical threshold is in the region
of 2 volts, but the actual value of the detected
threshold depends on the way in which VDD rises.
The POR circuit is NOT designed to supervise
static, or slowly rising or falling VDD.
3.2.5 MCU Initialization Sequence
When a reset occurs the stack is reset, the PC is
loaded with the address of the Reset Vector (lo-
cated in program ROM starting at address
0FFEh). A jump to the beginning of the user pro-
gram must be coded at this address. Following a
Reset, the Interrupt flag is automatically set, so
that the CPU is in Non Maskable Interrupt mode;
this prevents the initialisation routine from being
interrupted. The initialisation routine should there-
fore be terminated by a RETI instruction, in order
to revert to normal mode and enable interrupts. If
no pending interrupt is present at the end of the in-
itialisation routine, the MCU will continue by
processing the instruction immediately following
the RETI instruction. If, however, a pending inter-
rupt is present, it will be serviced.
Figure 11. Reset and Interrupt Processing
Figure 12. Reset Block Diagram
RESET
RESET
VECTOR
JP
JP:2 BYTES/4 CYCLES
RETI
RETI: 1 BYTE/2 CYCLES
INITIALIZATION
ROUTINE
VA00181
VDD
RESET
300k
2.8k
POWER
WATCHDOG RESET
CK
COUNTER
RESET
ST6
INTERNAL
RESET
fOSC
RESET
ON RESET
VA0200B
19



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