ST62T52B datasheet(27/68 Pages) STMICROELECTRONICS

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ST62T52B ST62T62B/E62B

IINTERRUPTS (Cont’d)

3.4.3 Interrupt Option Register (IOR)

The Interrupt Option Register (IOR) is used to en-

able/disable the individual interrupt sources and to

select the operating mode of the external interrupt

inputs. This register is write-only and cannot be

accessed by single-bit operations.

Address: 0C8h

—

Write Only

Reset status: 00h

Bit 7, Bits 3-0 = Unused.

Bit 6 = LES: Level/Edge Selection bit.

When this bit is set to one, the interrupt source #1

is level sensitive. When cleared to zero the edge

sensitive mode for interrupt request is selected.

Bit 5 = ESB: Edge Selection bit.

The bit ESB selects the polarity of the interrupt

source #2.

Bit 4 = GEN: Global Enable Interrupt. When this

bit is set to one, all interrupts are enabled. When

this bit is cleared to zero all the interrupts (exclud-

ing NMI) are disabled.

When the GEN bit is low, the NMI interrupt is ac-

tive but cannot cause a wake up from STOP/WAIT

modes.

This register is cleared on reset.

3.4.4 Interrupt Sources

Interrupt

sources

available

the

ST62E62B/T62B are summarized in the Table 10

with associated mask bit to enable/disable the in-

terrupt request.

Table 10. Interrupt Requests and Mask Bits

LES

ESB

GEN

Peripheral

Address

Mask bit

Masked Interrupt Source

Interrupt

vector

GENERAL

IOR

C8h

GEN

All Interrupts, excluding NMI

TIMER

TSCR1

D4h

ETI

TMZ: TIMER Overflow

Vector 4

A/D CONVERTER

ADCR

D1h

EAI

EOC: End of Conversion

Vector 4

AR TIMER

ARMC

D5h

OVIE

CPIE

EIE

OVF: AR TIMER Overflow

CPF: Successful compare

EF: Active edge on ARTIMin

Vector 3

Port PAn

ORPA-DRPA

C0h-C4h

ORPAn-DRPAn

PAn pin

Vector 1

Port PBn

ORPB-DRPB

C1h-C5h

ORPBn-DRPBn

PBn pin

Vector 1

Port PCn

ORPC-DRPC

C2h-C6h

ORPCn-DRPCn

PCn pin

Vector 2

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