ST6255CB3 datasheet(54/86 Pages) STMICROELECTRONICS

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ST62T55C ST62T65C/E65C

4.5 SERIAL PERIPHERAL INTERFACE (SPI)

The SPI peripheral is an optimized synchronous

serial interface with programmable transmission

modes and master/slave capabilities supporting a

wide range of industry standard SPI specifications.

The SPI interface may also implement asynchro-

nous data transfer, in which case processor over-

head is limited to data transfer from or to the shift

The SPI may be controlled by simple user soft-

ware to perform serial data exchange with low-

cost external memory, or with serially controlled

peripherals to drive displays, motors or relays.

The SPI’s shift register is simultaneously fed by

the Sin pin and feeds the Sout pin, thus transmis-

sion and reception are essentially the same proc-

ess. Suitable setting of the number of bits in the

data frame can allow filtering of unwanted leading

data bits in the incoming data stream.

The SPI comprises an 8-bit Data/Shift Register,

DSR, a Divide register, DIV, a Mode Control Reg-

ister MOD, and a Miscellaneous register, MISCR.

The SPI may be operated either in Master mode or

in Slave mode.

Master mode is defined by the synchronous serial

clock being supplied by the MCU, by suitably pro-

gramming the clock divider (DIV register). Slave

mode is defined by the serial clock being supplied

externally on the SCK pin by the external Master

device.

For maximum versatility the SPI may be pro-

grammed to sample data either on the rising or on

the falling edge of SCK, with or without phase shift

(clock Polarity and Phase selection).

The Sin, Sout and SCK signals are connected as

alternate I/O pin functions.

For serial input operation, Sin must be configured

as an input. For serial output operation, Sout is se-

lected as an output by programming Bit 0 of the

Miscellaneous Register: clearing this bit will set

the pin as a standard I/O line, while setting the bit

will select the Sout function.

An interrupt request may be associated with the

end of a transmission or reception cycle; this is de-

fined by programming the number of bits in the

data frame and by enabling the interrupt. This re-

quest is associated with interrupt vector #2, and

can be masked by programming the SPIE bit of

the MOD register. Since the SPI interrupt is

“ORed” with the port interrupt source, an interrupt

flag bit is available in the DIV register allowing dis-

crimination of the interrupt request.

Figure 30. SPI Block Diagram

SPI

SCK

FILTER

Sin

Sout

CPU

CYCLE

CLOCK

DATA BUS

VR001693

SHIFT

FILTER

DIVIDER

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