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ST72311R 数据表(PDF) 32 Page - STMicroelectronics |
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ST72311R 数据表(HTML) 32 Page - STMicroelectronics |
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32 / 164 page  ST72311R, ST72511R, ST72512R, ST72532R 32/164 INTERRUPTS (Cont’d) Table 6. Dedicated Interrupt Instruction Set Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions. In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions should never be used in an interrupt routine. Table 7. Interrupt Mapping Instruction New Description Function/Example I1 H I0 N Z C HALT Entering Halt mode 1 0 IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C JRM Jump if I1:0=11 I1:0=11 ? JRNM Jump if I1:0<>11 I1:0<>11 ? POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0 SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1 TRAP Software trap Software NMI 1 1 WFI Wait for interrupt 1 0 N ° Source Block Description Register Label Priority Order Exit from HALT Address Vector RESET Reset N/A Highest Priority Lowest Priority yes FFFE h-FFFFh TRAP Software Interrupt no FFFCh-FFFDh 0 TLI External Top Level Interrupt MISCR2 yes FFFA h-FFFBh 1 MCC/RTC Main Clock Controller Time Base Interrupt MCCSR FFF8h-FFF9h 2 ei0 External Interrupt Port A3..0 N/A FFF6h-FFF7h 3 ei1 External Interrupt Port F2..0 FFF4h-FFF5h 4 ei2 External Interrupt Port B3..0 FFF2h-FFF3h 5 ei3 External Interrupt Port B7..4 FFF0h-FFF1h 6 CAN CAN Peripheral Interrupts CANISR FFEEh-FFE Fh 7 SPI SPI Peripheral Interrupts SPISR no FFECh-FFE Dh 8 TIMER A TIMER A Peripheral Interrupts TASR FFEAh-FFEBh 9 TIMER B TIMER B Peripheral Interrupts TBSR FFE8h-FFE 9h 10 SCI SCI Peripheral Interrupts SCISR FFE6h-FFE 7h 11 EEPROM EEPROM Interrupt EECSR FFE4h-FFE 5h 12 Not Used FFE2h-FFE 3h 13 PWM ART PWM ART Overflow Interrupt ARTCSR Yes FFE0h-FFE 1h |
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