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ST72311R 数据表(PDF) 45 Page - STMicroelectronics |
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ST72311R 数据表(HTML) 45 Page - STMicroelectronics |
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45 / 164 page  ST72311R, ST72511R, ST72512R, ST72532R 45/164 9 MISCELLANEOUS REGISTERS The miscellaneous registers allow control over several features such as the external interrupts or the I/Oalternate functions. 9.1 I/O PORT INTERRUPT SENSITIVITY The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the Miscellaneous registers (Figure 27). This control allows to have up to 4 fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four (or five) different events on the pin: s Falling edge s Rising edge s Falling and rising edge s Falling edge and low level s Rising edge and high level (only for ei0 and ei2) To guarantee correct functionality, the sensitivity bits in the MISCR registers must be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). See I/O port register and Miscel- laneous register descriptions for more details on the programming. 9.2 I/O PORT ALTERNATE FUNCTIONS The MISCR registers allow to manage four I/O port miscellaneous alternate functions: s Main clock signal (fOSC/2) output on PF0 s A Beep signal output on PF1 (with three selectable audio frequencies) s A TLI management on a dedicated pin s A SPI SS pin internal control to use the PC7 I/O port function while the SPI is active. These functions are described in details in the Section 9.3 ”MISCELLANEOUS REGISTERS” on page 46. Figure 27. External Interrupt Sources vs MISCR ei0 INTER RUPT SOURCE ei1 INTERRUPT SOURCE IS20 IS21 MISCR1 SENSI TIVITY CONTROL PA3 PA2 MISCR2.IPA PA1 PA0 PF2 PF1 PF0 ei2 INTERRUPT SOURCE ei3 INTERRUPT SOURCE IS10 IS11 MISCR1 SENSI TIVITY CONTROL PB3 PB2 MISCR2.IPB PB1 PB0 PB7 PB6 PB5 PB4 SOURCES SOURCES SOURCES SOURCES |
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