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ST72521 数据表(PDF) 55 Page - STMicroelectronics |
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ST72521 数据表(HTML) 55 Page - STMicroelectronics |
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55 / 211 page  ST72521 55/211 WATCHDOG TIMER (Cont’d) Figure 34. Exact Timeout Duration (tmin and tmax) WHERE: tmin0 = (LSB + 128) x 64 x tOSC2 tmax0 = 16384 x tOSC2 tOSC2 = 125ns if fOSC2=8 MHz CNT = Value of T[5:0] bits in the WDGCR register (6 bits) MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits in the MCCSR register To calculate the minimum Watchdog Timeout (tmin): IF THEN ELSE To calculate the maximum Watchdog Timeout (tmax): IF THEN ELSE Note: In the above formulae, division results must be rounded down to the next integer value. Example: With 2ms timeout selected in MCCSR register TB1 Bit (MCCSR Reg.) TB0 Bit (MCCSR Reg.) Selected MCCSR Timebase MSB LSB 0 0 2ms 4 59 0 1 4ms 8 53 1 0 10ms 20 35 1 1 25ms 49 54 Value of T[5:0] Bits in WDGCR Register (Hex.) Min. Watchdog Timeout (ms) tmin Max. Watchdog Timeout (ms) tmax 00 1.496 2.048 3F 128 128.552 CNT MSB 4 ------------- < t min t min0 16384 CNT t osc2 × × + = t min t min0 16384 CN T 4 CNT MSB ----------------- – × 192 LS B + () 64 4CNT MSB ----------------- × × + t osc2 × + = CNT MSB 4 ------------- ≤ t ma x t max0 16384 C NT t osc2 × × + = t max t max0 16384 C NT 4CNT MSB ----------------- – × 192 LSB + () 64 4CNT MSB ----------------- × × + t osc2 × + = |
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