ST7265X datasheet(71/166 Pages) STMICROELECTRONICS

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ST7265x

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USB INTERFACE (Cont’d)

11.3.7 Register Description

BUFFER

CONTROL/STATUS

(BUFCSR)

Read Only (except bit 0, read/write)

Reset Value: 0000 0000 (00h)

Bits 7:4 = Reserved, forced by hardware to 0.

Bit 3 = BUFNUM

Current USB Buffer Number

This bit is set and cleared by hardware. When data

are received by Endpoint 2 in normal mode (refer

to the description of the MOD[1:0] bits in the

EP2RXR register) it indicates which buffer con-

tains the data.

0: Current buffer is Buffer 0

1: Current buffer is Buffer 1

Bits 2:1 = STATB[1:0]

Buffer Status Bits

These bits are set and cleared by hardware. When

data are transmitted or received by Endpoint 2 in

upload or download mode (refer to the description

of the MOD[1:0] bits in the EP2RXR register) the

STATB[1:0] bits indicate the status as follows:

Bit 0 = CLR

Clear Buffer Status

This bit is written by software to clear the BUF-

NUM and STATB[1:0] bits (it also resets the pack-

et counter of the Buffer Manager state machine). It

can be used to re-initialize the upload/download

flow (refer to the description of the MOD[1:0] bits in

the EP2RXR register).

0: No effect

1: Clear BUFNUM and STATB[1:0] bits

INTERRUPT STATUS REGISTER (ISTR)

Read/Write

Reset Value: 0000 0000 (00h)

These bits cannot be set by software. When an in-

terrupt occurs these bits are set by hardware. Soft-

ware must read them to determine the interrupt

type and clear them after servicing.

Note: The CTR bit (which is an OR of all the end-

point CTR flags) cannot be cleared directly, only

by clearing the CTR flags in the Endpoint regis-

ters.

Bit 7 = CTR

Correct Transfer.

This bit is set by hardware when a correct transfer

operation is performed. This bit is an OR of all

CTR flags (CTR0 in the EP0R register and

CTR_RX and CTR_TX in the EPnR registers). By

looking in the USBSR register, the type of transfer

can be determined from the PID[1:0] bits for End-

point 0. For the other Endpoints, the Endpoint

number on which the transfer was made is identi-

fied by the EP[1:0] bits and the type of transfer by

the IN/OUT bit.

0: No Correct Transfer detected

1: Correct Transfer detected

Note: A transfer where the device sent a NAK or

STALL handshake is considered not correct (the

host only sends ACK handshakes). A transfer is

considered correct if there are no errors in the PID

and CRC fields, if the DATA0/DATA1 PID is sent

as expected, if there were no data overruns, bit

stuffing or framing errors.

Bit 6 = Reserved, forced by hardware to 0.

Bit 5 = SOVR Setup Overrun.

This bit is set by hardware when a correct Setup

transfer operation is performed while the software

is servicing an interrupt which occurred on the

same Endpoint (CTR0 bit in the EP0R register is

still set when SETUP correct transfer occurs).

0: No SETUP overrun detected

1: SETUP overrun detected

When this event occurs, the USBSR register is not

updated because the only source of the SOVR

event is the SETUP token reception on the Control

Endpoint (EP0).

BUF-

NUM

STAT

CLR

Meaning

STATBn

Value

Upload

Mode

Buffer n not full (USB waiting to

read Buffer n)

Buffer n full (USB can upload this

buffer)

Download

Mode

Buffer n empty (Can be written to

by USB)

Buffer n not empty (USB waiting

to write to this buffer)

CTR

SOVR ERROR SUSP ESUSP RESET SOF

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